CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 100

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.4.2.3
Each physical memory region to be transferred is
described by a Physical Region Descriptor (PRD) as illus-
trated in Table 5-8. When the bus master is enabled (Com-
mand register bit 0 = 1), data transfer proceeds until each
PRD in the PRD table has been transferred. The bus mas-
ter does not cache PRDs.
The PRD table consists of two DWORDs. The first
DWORD contains a 32-bit pointer to a buffer to be trans-
ferred. This pointer must be WORD aligned. The second
DWORD contains the size (16 bits) of the buffer and the
EOT (End Of Table) flag. The size must be in multiples of
one WORD (2 bytes) or zero (meaning a 64 KB transfer).
The EOT bit (bit 31) must be set to indicate the last PRD in
the PRD table.
5.4.2.4
The following steps explain how to initiate and maintain a
bus master transfer between memory and an IDE device:
1)
100
DWORD
Software creates a PRD table in system memory.
Each PRD entry is 8 bytes long, consisting of a base
address pointer and buffer size. The maximum data
that can be transferred from a PRD entry is 64 KB. A
PRD table must be aligned on a 4-byte boundary. The
last PRD in a PRD table must have the EOT bit set.
0
1
Physical Region Descriptor Format
Programming Model
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Byte 3
31506B
Table 5-8. Physical Region Descriptor Format
Reserved
Memory Region Physical Base Address [31:1] (IDE Data Buffer)
Byte 2
2)
3)
4)
5)
6)
7)
8)
Software loads the starting address of the PRD table
by programming the PRD Table Address register.
Software must fill the buffers pointed to by the PRDs
with IDE data.
Write 1 to the Bus Master Interrupt bit and Bus Master
Error (Status register bits 2 and 1) to clear the bits.
Set the correct direction to the Read or Write Control
bit (Command register bit 3).
Engage the bus master by writing a 1 to the Bus Mas-
ter Control bit (Command register bit 0).
The bus master reads the PRD entry pointed to by the
PRD Table Address register and increments the
address by 08h to point to the next PRD. The transfer
begins.
The bus master transfers data to/from memory
responding to bus master requests from the IDE
device until all PRD entries are serviced.
The IDE device signals an interrupt once its pro-
grammed data count has been transferred.
In response to the interrupt, software resets the Bus
Master Control bit in the Command register. It then
reads the status of the controller and IDE device to
determine if the transfer is successful.
AMD Geode™ CS5535 Companion Device Data Book
Byte 1
Size [15:1]
8
7
6
5
Byte 0
4
ATA-5 Controller
3
2
1
0
0
0