CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 102

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.5
The two Universal Serial Bus Controllers (USBC) each
contain a GeodeLink™ Adapter, PCI Adapter, and USB
Core blocks. The functional descriptions of the blocks are
described in the following subsections.
5.5.1
The GeodeLink Adapter (GLA) translates GeodeLink trans-
actions to/from Local bus transactions. The GLA interfaces
to a 64-bit GLIU (GeodeLink Interface Unit) and a 32-bit
Local bus. The GLA supports in-bound memory and I/O
requests which are converted by the PCI Adapter (PA) into
PCI memory and I/O requests that target the USBC. It also
supports in-bound MSR transactions to the MSRs. These
are located “between” the GLA and PA. Lastly, there is a
special MSR used to pass PCI configuration requests to
the PA. The GLA supports out-bound memory requests
only. I/O and MSR transactions from the USBC never
occur. USBC PCI master requests are converted by the PA
into Local bus master requests. These requests may con-
sist of a simple 4-byte read or write. Alternatively, a PCI
burst transaction of any length may be converted to an
102
Universal Serial Bus Controller
GeodeLink™ Adapter
USB
Interface
Frame Mgmnt
Control
Root
PCI Config
Hub
Interrupts
31506B
USB Port 1
Port 1
PCI
Interface
Figure 5-8. USB Core Block Diagram
PCI Slave
Processor
PCI I/O
List
SIE
appropriate series of GLIU transactions by the GLA. Lastly,
the GLA synchronizes GLIU transactions at the GLIU clock
to the slower Local bus transaction at Local bus clock.
5.5.2
The PCI Adapter translates PCI signals to a specific Local
bus transaction that is attached to the GLA, while the PCI
signals are connected directly to a compatible PCI device.
It also translates the Local bus transactions to PCI transac-
tions.
5.5.3
The USB Core is a PCI-based implementation of the Uni-
versal Serial Bus (USB) v1.1 Specification utilizing the
Open Host Controller Interface (OHCI) standard developed
by Compaq, Microsoft
USB Core consists of the three blocks: Host Controller,
USB Interface, and PCI Interface
The USB Core block diagram is shown in Figure 5-8.
Embedded PCI Bus
AMD Geode™ CS5535 Companion Device Data Book
PCI Adapter
USB Core
Generator
Port 2
Clock
USB Port 2
Host Controller
®
, and National Semiconductor. The
PCI Master
Data Buffer
Universal Serial Bus Controller
Master
Bus