CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 105

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Diverse Integration Logic
• Address Decode - Decodes the upper Local bus
• Standard MSRs - Includes the Standard GeodeLink
• Local BARs - Local Base Address Registers (LBARs)
• Data Out Mux (DOM) - This mux is not explicitly illus-
5.6.1
The LBARs are used to establish the address and hence,
chip select location of all functions that do not have fixed
legacy addresses. This block also has comparators to
establish when a current bus cycle address hits an LBAR.
A hit is passed to the address decode block and results in a
chip select to the target device if there are no conflicts. The
AMD Geode™ CS5535 Companion Device Data Book
Notes:
1)
2)
address bits to select a target slave. Most of the legacy
devices have fixed addresses or are selectable between
a small number of selectable I/O addresses. However,
many of the functions are relocatable via a Local Base
Address Register (LBAR); established via an MSR.
Address Decode also detects special GLIU cycles, such
as Shutdown, and takes appropriate action.
Device MSRs found in all GeodeLink Devices: Capabili-
ties, Master Configuration, SMI Control, Error Control,
Power Management, and Diagnostics.
establish the location of non-legacy functions within the
Diverse Device. The module also includes logic to
compare the current bus cycle address to the LBAR to
detect a hit. For the I/O LBARs, the I/O address space
000h-4FFh is off limits. No I/O LBAR is allowed to point
to this space.
trated. Each function above produces a single output to
the DIVIL. The DIVIL DOM has a port for each of the
functions and is responsible for selecting between them.
ADDR[15:12]
The I/O mask is always 4 bits.
The I/O base address is variable ([15:n]).
The value of “n” depends on the I/O space requirements of the target. For example, a device needing 4, 8, 16, 32,
64, 128, or 256 bytes of I/O space has “n” = 2, 3, 4, 5, 6, 7, 8, respectively. The value “n” for various functions is:
LBARs and Comparators
MSR_LBAR_IRQ
MSR_LBAR_GPIO
MSR_LBAR_ACPI
MSR_LBAR_FLASH_IO
I/O_MASK
Figure 5-11. I/O Space LBAR - Fixed Target Size
n = 5
n = 8
n = 5
n = 4
[15:12]
MSR_LBAR_SMB
MSR_LBAR_MFGPT
MSR_LBAR_PMS
Compare
mask and base address values are established via an
MSR.
5.6.1.1
This discussion applies to the following LBARs:
• MSR 51400008h: IRQ Mapper (MSR_LBAR_IRQ)
• MSR 5140000Bh: SMB (MSR_LBAR_SMB)
• MSR 5140000Ch: GPIO and ICFs (MSR_LBAR_GPIO)
• MSR 5140000Dh: MFGPTs (MSR_LBAR_MFGPT)
• MSR 5140000Eh: ACPI (MSR_LBAR_ACPI)
• MSR 5140000Fh: Power Management Support
The IO_MASK only applies to the upper bits [15:12] (see
Figure 5-11). Normally, one would set all the mask bits
(i.e., no mask on upper bits). One should only mask or
clear bits if address wrapping or aliasing is desired.
• Rule. When a mask bit is cleared, the associated bit in
The base size is fixed based on the target. For example,
the GPIO takes 256 bytes of address space. Therefore, the
base only applies to bits [15:8]. Base bits [7:0] are always
cleared by the hardware. Therefore, the base is always
forced by hardware to be on a boundary the size of the tar-
get.
(MSR_LBAR_PMS)
the base address must also be cleared. Otherwise, the
compare will not be equal on these bits. This rule
applies to both memory and I/O LBARs.
Hit
Fixed Target Size I/O LBARs
[15:n]
n = 3
n = 6
n = 7
31506B
BASE_ADDR
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