CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 115

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Programmable Interrupt Control
As illustrated in Figure 5-20, the blocks that make up the
8259A PIC are:
• Read/Write Control Logic
• Interrupt Request Register (IRR)
• In-Service Register (ISR)
• Interrupt Mask Register (IMR)
• Priority Resolver
• Interrupt Sequence
• Data Bus Buffer
• Cascade Buffer/Comparator
Read/Write Control Logic
The function of this block is to accept commands from the
CPU. It contains the four Initialization Command Word reg-
isters, ICW1-ICW4, and three Operation Command Word
registers, OCW1-OCW3, that can be programmed to oper-
ate in various modes.
IRR, ISR, and IMR
Three registers are available to handle interrupts in the
PIC: Interrupt Request Register (IRR), In-Service Register
(ISR), and Interrupt Mask Register (IMR). Each of the three
AMD Geode™ CS5535 Companion Device Data Book
D7-D0
SP/EN
CAS0
CAS1
CAS2
WR
RD
CS
A0
Comparator
Cascade
Buffer/
Read/
Buffer
Write
Logic
Data
Bus
Figure 5-20. PIC 8259A Block Diagram
Internal Bus
In-Service
Register
(ISR)
registers is eight bits wide, where every bit corresponds to
one of the IR0-IR7 input lines.
Priority Resolver
The priority resolver block manages the hardware requests
according to their priority. As several bits may be set in the
IRR simultaneously, the priority encoder passes only the
highest priority bit; ordered in priority 0 through 7 (0 being
the highest).
Interrupt Sequence
The INT output goes directly to the CPU interrupt input.
When an INT signal is activated, the CPU responds with an
Interrupt Acknowledge access that is translated to two
pulses on the INTA input of the PIC. At the first INTA pulse
the highest priority IRR bit is loaded into the corresponding
ISR bit, and that IRR bit is reset. The second INTA pulse
instructs the PIC to present the 8-bit vector of the interrupt
handler onto the data bus.
Data Bus Buffer
Control words and status information are transferred
through the data bus buffer.
Cascade Buffer/Comparator
This functional block stores and compares the IDs of the
PICs.
INTA
Interrupt Mask Register
Control Logic
Resolver
(IMR)
Priority
INT
31506B
Interrupt
Request
Register
(IRR)
IR0
IR1
IR2
IR3
IR4
IR5
IR6
IR7
115