CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 116

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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5.8.3.1
There are three registers in the PIC that control the inter-
rupt requests: Interrupt Request Register (IRR), Interrupt
Service Register (ISR), and Interrupt Mask Register (IMR).
The eight interrupt lines IR0-IR7 are connected to the IRR.
The peripheral that requests an interrupt raises the signal
at the corresponding IR0-IR7 inputs, which sets the corre-
sponding bit in the IRR. Several peripheral devices can
issue interrupt requests at the same time. The PIC gates
these requests under the Interrupt Mask register and under
the priority of any interrupt service routine already entered
(using the ISR), and activates the PIC’s output INTR to the
CPU. The CPU acknowledges the INTR, generating two
INTA pulses. On the first, the priority encoder transfers
(clears) the highest-priority enabled bit in the IRR to the
corresponding bit in the ISR (sets). Also, the two PICs use
their Cascade connections to decide which one will be
selected to respond further. On the second INTA pulse, the
selected PIC presents the 8-bit pointer (called as vector
data) onto the data bus. The CPU reads this pointer as the
number of the interrupt handler to call.
Software writes a command (EOI) at the end of the inter-
rupt subroutine, which clears the appropriate ISR bit.
Initialization and Programming
Two types of command words are generated by the CPU to
program the PIC:
1)
2)
ICWs and OCWs must be programmed before operation
begins.
Since both the PICs are cascaded, the ICW3 of the master
PIC should be programmed with the value 04h, indicating
that the IRQ2 input of the master PIC is connected to the
INT output of the slave PIC, rather than the I/O device. This
is part of the system initialization code. Also, ICW3 of the
slave PIC should be programmed with the value 02h (slave
ID) as that corresponds to the input on the master PIC.
For accessing the PIC’s registers, two ports are available
for the master and slave. Table 5-15 lists the addresses
and read/write data for these registers.
116
Initialization Command Word (ICW): The PIC is first
initialized by four ICWs (ICW1-ICW4) before any nor-
mal operation begins. The sequence is started by writ-
ing Initialization Command Word 1 (CW1). After ICW1
has been written, the controller expects the next writes
to follow in the sequence ICW2, ICW3, and ICW4 if it
is needed.
Operation Command Word (OCW): Using these
three OCWs (OCW1-OCW3), the PIC is instructed to
operate in various interrupt modes. These registers
can be written after the initialization above.
Interrupt Sequence
31506B
Table 5-15. 8259A PIC I/O Addresses and I/O Data
5.8.3.2
Fully Nested Mode
The interrupt requests are ordered in priority from 0
through 7.
The highest priority request is processed and its vector
data placed on the bus.
The corresponding ISR bit is set until the trailing edge of
the last INTA. While the ISR bit is set, all other interrupts of
the same or lower priority are inhibited, while higher levels
will be acknowledged only if the CPU’s internal interrupt
enable flip-flop has been re-enabled through software.
End of Interrupt (EOI) Mode
The ISR bit can be reset by a command word that must be
issued to the PIC before returning from a service routine.
EOI must be issued twice if in cascade mode, once for the
master and once for the slave.
There are two forms of EOI: Specific and Non-Specific.
When a non-specific EOI is issued, the PIC automatically
resets the ISR bit corresponding to the highest priority level
in service. A non-specific EOI can be issued with OCW2
(EOI = 1, SL = 0, R = 0).
A specific EOI is issued when a mode is used that may dis-
turb the fully nested structure and the PIC might not be
able to determine the last interrupt level acknowledged. A
specific EOI can be issued with OCW2 (EOI = 1, SL = 1, R
= 0, and L0-L2 is the binary level of the ISR bit to be reset).
Automatic End of Interrupt (AEOI) Mode
The PIC automatically performs a non-specific EOI at the
trailing edge of the last INTA pulse. This mode is not sup-
ported in the Geode CS5535 companion device.
I/O Address
IRQ0-IRQ7
(Master)
020h
021h
AMD Geode™ CS5535 Companion Device Data Book
Interrupt Modes
I/O Address
IRQ8-IRQ15
(Slave)
0A0h
0A1h
Programmable Interrupt Control
Read
Data
IMR
IRR
ISR
OCW1 (IMR)
OCW2
OCW3
Write
ICW1
ICW2
ICW3
ICW4
Data

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