CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 117

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Programmable Interrupt Control
Automatic Rotation Mode
In cases where a number of IRQs have equal priority, the
device that has been serviced, will receive the lowest prior-
ity. So now that device, if requesting another interrupt,
must wait until the other seven devices have been ser-
viced.
There are two ways to accomplish automatic rotation using
OCW2:
• Rotation on the non-specific EOI command (R = 1, SL =
• Rotation in automatic EOI mode, which is set by (R = 1,
Specific Rotation Mode
Priorities can be changed by programming the bottom pri-
ority, which fixes all other priorities. For example, if IR5 is
programmed as the bottom priority device, then IR6 will
have the highest priority. The command is issued to OCW2
(R = 1, SL = 1, and L0-L2 is the binary priority level code of
the bottom priority device).
Special Mask Mode
In this mode, when a mask bit is set in OCW1, it inhibits
further interrupts at that level and enables interrupts from
all other levels (lower as well as higher) that are not
masked. The special mask mode is set (SSMM = 1, SMM =
1) and cleared (SSMM = 1, SMM = 0) by OCW3.
5.8.4
From reset, the PIC subsystem comes up in legacy mode.
The “Primary” mapper and mask inputs connect directly to
LPIC and all other interrupt sources are masked off.
While there are a number of different ways to use the PIC
Subsystem, the discussions that follow assume a mix of
“level” and “edge” interrupt inputs. The first discussion
assumes the OS schedules the “work” of the interrupt ser-
vice after a brief interrupt service routine. The second dis-
cussion assumes the OS performs the “work” real-time in
the interrupt service routine.
Assume the mapper and masks have been established as
desired. “Level” interrupts can be shared, but “edge” inter-
rupts cannot. This means an XPIC “level” output can be
driven by up to four mapper and masks inputs. Further, this
means an XPIC “edge” output can only be driven by one
mapper and mask input.
Assume all edge interrupts generate a low-to-high edge to
indicate an interrupt. Assume active low interrupts are
inverted outside the PIC subsystem as needed; that is, all
MM inputs are active high. An external PCI bus uses active
low interrupts that can be shared in an open-collector wired
“OR” fashion. This is OK. On-chip, the interrupt sense is
inverted. Lastly, note that for the edge interrupts the edge
must remain high until the interrupt acknowledge action.
AMD Geode™ CS5535 Companion Device Data Book
0, EOI = 1).
SL = 0, EOI = 0) and cleared by (R = 0, SL = 0, EOI = 0).
PIC Subsystem Operation
Assume LPIC is initialized as follows:
;Set Initialization Command Words (ICWs)
;All values are in hex
;PIC #1 (Master)
out 20, 11
out 21, 8
out 21, 4
out 21, 1
out 21, ff
;PIC #2 (Slave)
out a0, 11
out a1, 70
out a1, 2
out a1, 1
out a1, ff
;Use Operation Control Words (OCWs) during interrupt
service
Thus, the LPIC 8259As all start in edge mode. This is fol-
lowed by writes to the individual edge level registers at
4D0h (interrupts 0-7) and 4D1h (interrupts 8-15) to estab-
lish level mode for all level inputs. Note that IRQ0 and
IRQ2 can not be put in level mode. Writing 0FFh to 4D0h
will read back 0FAh.
Scheduled Interrupts Approach
The following set of events would be typical. Assume the
processor has maskable interrupts enabled:
1)
2)
3)
4)
5)
One or more interrupts are generated in the system.
These set the associated bits in the LPIC Interrupt
Request Register (IRR).
The maskable interrupt signal (INTR) is asserted by
the LPIC and interrupts the processor. INTR is an
active high level.
The processor generates an interrupt acknowledge
bus cycle that flows through the GeodeLink™ system
as a single BIZZARO packet. When it reaches the
Diverse Logic, it is converted to the two cycle interrupt
acknowledge sequence expected by the LPIC.
The acknowledge operation returns an interrupt vector
to the processor that is used to call the appropriate
interrupt service routine. Processor interrupts are now
disabled at the processor.
The acknowledge operation also selects the highest
priority interrupt from the IRR and uses it to set one bit
in the LPIC Interrupt Service Register (ISR). Each
acknowledge operation always sets a single ISR bit.
; ICW3 - Slave Level 2
; ICW4 - Slave, 8086 mode
; ICW1 - Edge, Master, ICW4 needed
; ICW2 - Interrupt vector table offset is 8
; ICW3 - Master level 2
; ICW4 - Master, 8086 mode
; mask all IRQs
; ICW1 - Edge, Slave ICW4 needed
; ICW2 - Interrupt vector table offset 70
; mask all IRQs
31506B
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