CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 121

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Direct Memory Access Module
5.9.6
The Diverse Integration Logic module contains shadow
registers (see Section 6.13 on page 417) for reading the
configuration of the DMA controllers.
5.9.7
DMA transfers occur over the entire 32-bit address range
of the PCI bus. This is accomplished by using the DMA
controller’s 16-bit memory address registers in conjunction
with an 8-bit DMA Low Page register and an 8-bit DMA
High Page register. These registers, associated with each
channel, provide the 32-bit memory address capability. A
write to the Low Page register clears the High Page regis-
ter, for backward compatibility with the PC/AT standard.
The starting address for the DMA transfer must be pro-
grammed into the DMA controller registers and the chan-
nel’s respective Low and High Page registers prior to
beginning the DMA transfer.
DMA Page Registers and Extended Addressing
The DMA Page registers provide the upper address bits
during DMA cycles. DMA addresses do not increment or
decrement across page boundaries. Page boundaries for
the 8-bit channels (Channels 0 through 3) are every 64 KB
and page boundaries for the 16-bit channels (Channels 5,
6, and 7) are every 128 KB.
Before any DMA operations are performed, the Page regis-
ters must be written at the I/O Port addresses in the DMA
controller registers to select the correct page for each DMA
channel. The other address locations between 080h and
08Fh and 480h and 48Fh are not used by the DMA chan-
nels, but can be read or written by a PCI bus master.
These registers are reset to zero at POR. A write to the
Low Page register clears the High Page register, for back-
ward compatibility with the PC/AT standard.
For most DMA transfers, the High Page register is set to
zeros and is driven onto PCI address bits AD[31:24] during
DMA cycles. This mode is backward compatible with the
PC/AT standard. For DMA extended transfers, the High
Page register is programmed and the values are driven
onto the PCI addresses AD[31:24] during DMA cycles to
allow access to the full 4 GB PCI address space.
5.9.8
The DMA addresses are formed such that there is an
upper address, a middle address, and a lower address por-
tion.
The upper address portion, which selects a specific page,
is generated by the Page registers. The Page registers for
each channel must be set up by the system before a DMA
operation. The DMA Page register values are driven on
PCI address bits AD[31:16] for 8-bit channels and
AD[31:17] for 16-bit channels.
AMD Geode™ CS5535 Companion Device Data Book
DMA Shadow Registers
DMA Addressing Capability
DMA Address Generation
The middle address portion, which selects a block within
the page, is generated by the DMA controller at the begin-
ning of a DMA operation and any time the DMA address
increments or decrements through a block boundary. Block
sizes are 256 bytes for 8-bit channels (Channels 0 through
3) and 512 bytes for 16-bit channels (Channels 5, 6, and
7). The middle address bits are driven on PCI address bits
AD[15:8] for 8-bit channels and AD[16:9] for 16-bit chan-
nels.
The lower address portion is generated directly by the
DMA controller during DMA operations. The lower address
bits are output on PCI address bits AD[7:0] for 8-bit chan-
nels and AD[8:1] for 16-bit channels.
5.9.9
For each 8-bit DMA channel, the DMA mapper allows the
DMA request to come from a number of sources. Table 5-
16 shows how the DMA mapper register select field selects
the appropriate DMA source.
When LPC is selected as the DMA source for DMA Chan-
nel 0, the source is LPC DMA Channel 0. Similarly, when
LPC is selected as the source for DMA Channel 1, 2, or 3,
then the DMA sources for those three DMA channels are
respectively LPC DMA Channels 1, 2, and 3. Therefore,
LPC DMA Channel 0 can only be mapped to DMA Channel
0, LPC DMA Channel 1 can only be mapped to DMA Chan-
nel 1, etc.
Source Selector
Value from DMA
Mapper
Table 5-16. DMA Source Selection
DMA Mapper Source Selection
0
1
2
3
4
5
6
7
DMA Source
None (DMA channel off)
UART1 Transmit
UART1 Receive
UART2 Transmit
UART2 Receive
Reserved (not active)
Reserved (not active)
LPC
31506B
121