CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 127

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

System Management Bus Controller
5.11
The System Management Bus (SMB) Controller is a two-
wire synchronous serial interface compatible with the Sys-
tem Management Bus physical layer. The SMB Controller
is also compatible with Intel's SMBus and Philips’ I
SMB Controller can be configured as a bus master or
slave, and can maintain bidirectional communication with
both multiple master and slave devices. As a slave device,
the SMB Controller may issue a request to become the bus
master.
The SMB Controller allows easy interfacing to a wide range
of low-cost memories and I/O devices, including:
EEPROMs, SRAMs, timers, ADC, DAC, clock chips, and
peripheral drivers.
This chapter describes the general SMB Controller func-
tional block. A device may include a different implementa-
tion.
A block diagram of the System Management Bus (SMB)
Controller is shown Figure 5-23.
The SMB Controller is upward compatible with previous
industry standard two-wire interfaces as detailed in Table
5-18 on page 128.
AMD Geode™ CS5535 Companion Device Data Book
System Management Bus Controller
Data In
Data In
Local Bus Interface
Figure 5-23. SMB Block Diagram
SMB Controller
2
C. The
Clock
CCU
The SMB Controller’s protocol uses a two-wire interface for
bidirectional communication between the ICs connected to
the bus. The two interface lines are the Serial Data Line
(SDL) and the Serial Clock Line (SCL). These lines should
be connected to a positive supply via an internal or external
pull-up resistor, and remain high even when the bus is idle.
Each IC has a unique address and can operate as a trans-
mitter or a receiver (though some peripherals are only
receivers).
During data transactions, the master device initiates the
transaction, generates the clock signal, and terminates the
transaction. For example, when the SMB Controller ini-
tiates a data transaction with an attached SMB compliant
peripheral, the SMB Controller becomes the master. When
the peripheral responds and transmits data to the SMB
Controller, their master/slave (data transaction initiator and
clock generator) relationship is unchanged, even though
their transmitter/receiver functions are reversed.
Busy
IRQ
PIC
31506B
I/O Enable
Data Out
Clock Out
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