CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 138

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.12.1
This section describes the operation modes of the
UART/IR Controller. Although each mode is unique, certain
system resources and features are common.
138
Bank 0
Bank 1
Bank 2
04-07h RSVD
Offset Name
00h
00h
01h
02h
03h
04h
05h
06h
07h
00h
01h
02h
03h
00h
01h
02h
03h
04h
05h
06h
07h
I/O
RXD
TXD
IER
(
IER
(
EIR
(Note 1)
EIR
(Note 2)
FCR
LCR
BSR
MCR
(Note 1)
MCR
(Note 2)
LSR
MSR
SPR
(Note 1)
ASCR
(Note 2)
LBGD_L
LBGD_H
RSVD
LCR
BSR
BGD_L
BGD_H
EXCR1
BSR
EXCR2
RSVD
TXFLV
RXFLV
Note 1
Note 2
Operational Modes
)
)
ER_INF
31506B
BKSE
BKSE
BKSE
LOCK
RXD7
TXD7
BKSE
BKSE
DCD
CTE
7
RXFTH[1:0]
Table 5-20. UART/IR Controller Native Register Bit Map
FEN[1:0]
RSVD
RSVD
RSVD
RSVD
RSVD
MDSL[2:0]
TXEMP
SBRK
RSVD
TXUR
SBRK
RSVD
RXD6
TXD6
RI
6
RSVD
TXEMP_EV
TXEMP_IE
EDTLBK
RXACT
TXRDY
RXD5
STKP
STKP
TXD5
DSR
5
TXFTH[1:0]
PRESL[1:0]
RSVD
DMA_EV
RXWDG
DMA_IE
IR_PLS
LOOP
LOOP
RXD4
TXD4
BRK
CTS
EPS
EPS
This discussion references several bits in the UART/IR
Controller Native register set. Table 5-20 provides the bit
map for the UART/IR Controller Native registers for the
reader’s convenience. For full bit descriptions, refer to Sec-
tion 6.12.2 on page 383.
4
Scratch Data
LBGD[15:8]
LBGD[7:0]
BGD[15:8]
BGD[7:0]
RSVD
RSVD
RSVD
AMD Geode™ CS5535 Companion Device Data Book
DMASWP
BSR[6:0]
BSR[6:0]
BSR[6:0]
TX_DFR
MS_EV
ISEN or
DCDLP
MS_IE
MS_IE
DDCD
RXD3
RSVD
RSVD
TXD3
RXFT
PEN
PEN
FE
3
RF_SIZ[1:0]
RFL[5:0]
TFL[5:0]
TXHLT_EV
DMA_EN
DMATH
LS_EV/
S_OET
RXD2
LS_IE
LS_IE
TXSR
TXD2
RILP
TERI
STB
STB
PE
2
IPR[1:0]
TXLDL_EV
TXLDL_IE
TXLDL_IE
DMANF
DDSR
RXSR
RSVD
WLS1
RXD1
TXD1
RTS
RTS
OE
1
TF_SIZ1[1:0]
WLS[1:0]
UART and IR Port
RXF_TOUT
RXHDL_IE
RXHDL_IE
RXHDL_IE
FIFO_EN
EXT_SL
RXDA
DCTS
WLS0
RXD0
TXD0
DTR
DTR
IPF
0