CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 142

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Oversampled mode can be used with the receiver demodu-
lator either enabled or disabled. It should be used with the
demodulator disabled when a detailed snapshot of the
incoming signal is needed; for example, to determine the
period of the carrier signal. If the demodulator is enabled,
the stream of samples can be used to reconstruct the
incoming bit-string. To obtain good resolution, a fairly high
sampling rate should be selected.
Programmed T Period mode should be used with the
receiver demodulator enabled. The T Period represents
one-half bit time for protocols using biphase encoding or
the basic unit of pulse distance for protocols using pulse
distance encoding. The baud is usually programmed to
match the T Period. For long periods of logic low or high,
the receiver samples the demodulated signal at the pro-
grammed sampling rate.
When a new IR energy pulse is detected, the receiver syn-
chronizes the sampling process to the incoming signal tim-
ing. This reduces timing-related errors and eliminates the
possibility of missing short IR pulse sequences, especially
with the RECS 80 protocol. In addition, the Programmed T
Period sampling minimizes the amount of data used to rep-
resent the incoming IR signal, therefore reducing the pro-
cessing overhead in the host CPU.
5.12.1.5 FIFO Timeouts
Timeout mechanisms are provided to prevent received
data from remaining in the RX_FIFO indefinitely, in case
the programmed interrupt or DMA thresholds are not
reached.
An RX_FIFO timeout generates a Receiver Data Ready
interrupt and/or a receiver DMA request if bit 0 of the IER
register and/or bit 2 of the MCR register (in Extended
mode) are set to 1, respectively. An RX_FIFO timeout also
sets bit 0 of the ASCR register to 1 if the RX_FIFO is below
the threshold. When a Receiver Data Ready interrupt
occurs, this bit is tested by the software to determine
whether a number of bytes indicated by the RX_FIFO
threshold can be read without checking bit 0 of the LSR
register.
The conditions that must exist for a timeout to occur in the
modes of operation are described below. When a timeout
has occurred, it can only be reset when the FIFO is read by
the processor or DMA controller.
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31506B
Timeout Conditions for UART, SIR, and Sharp-IR
Modes
RX_FIFO timeout conditions:
• At least one byte is in the RX_FIFO.
• More than four character times have elapsed since the
• More than four character times have elapsed since the
Timeout Conditions for CEIR Mode
The RX_FIFO timeout in CEIR mode is disabled while the
receiver is active. The conditions for this timeout to occur
are as follows:
• At least one byte has been in the RX_FIFO for 64 µs or
• The receiver has been inactive (RXACT = 0) for 64 µs or
• More than 64 µs have elapsed since the last byte was
5.12.1.6 Transmit Deferral
This feature allows software to send short, high-speed data
frames in PIO mode without the risk of generating a trans-
mitter underrun.
Transmit deferral is available only in extended mode and
when the TX_FIFO is enabled. When transmit deferral is
enabled (TX_DFR bit of the MCR register set to 1) and the
transmitter becomes empty, an internal flag is set and
locks the transmitter. If the processor now writes data into
the TX_FIFO, the transmitter does not start sending the
data until the TX_FIFO level reaches either 14 for a 16-
level TX_FIFO or 30 for a 32-level TX_FIFO, at which time
the internal flag is cleared. The internal flag is also cleared
and the transmitter starts transmitting when a timeout con-
dition is reached. This prevents some bytes from being in
the TX_FIFO indefinitely if the threshold is not reached.
The timeout mechanism is implemented by a timer that is
enabled when the internal flag is set and there is at least
one byte in the TX_FIFO. Whenever a byte is loaded into
the TX_FIFO, the timer is reloaded with the initial value. If
no byte is loaded for a 64 µs time, the timer times out and
the internal flag is cleared, thus enabling the transmitter.
last byte was loaded into the RX_FIFO from the receiver
logic.
last byte was read from the RX_FIFO by the processor
or DMA controller.
more.
more.
read from the RX_FIFO by the processor or DMA
controller.
AMD Geode™ CS5535 Companion Device Data Book
UART and IR Port