CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 147

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Low Pin Count Port
5.13.1
LPC supports memory read/write, I/O read/write, DMA
read/write, and Firmware Hub Interface (see Table 5-22).
Data transfers on the LPC bus are serialized over a 4-bit
bus.
LFRAME# is used by the host to start or stop transfers. No
peripherals drive this signal. A cycle is started by the host
when it drives LFRAME# active and puts information
related to the cycle on the LAD[3:0] signals. The host
drives information such as address or DMA channel num-
ber. For DMA and target cycles, the host drives cycle type
(memory or I/O), read/write direction, and size of the trans-
fer. The host optionally drives data, and turns around to
monitor peripherals for completion of the cycle. The periph-
eral indicates the completion of the cycle by driving appro-
priate values on the LAD[3:0] signals.
The LAD[3:0] signals communicate address, control, and
data information over the LPC bus between the host and
the peripheral. The information carried on the LAD signals
are: start, stop (abort a cycle), transfer type (memory, I/O,
DMA), transfer direction (read/write), address, data, wait
states, and DMA channel number. The following sections
give an overview of fields used. Detailed field descriptions
are provided in Table 5-23 on page 148.
START: This field indicates the start or stop of a transac-
tion. The START field is valid on the last clock that
LFRAME# is active. It is used to indicate a device number,
or start/stop indication.
CYCTYP: The Cycle Type field is driven by the host when
it is performing DMA or target accesses. Bits [3:2] are used
for cycle type and bit 1 is used for direction. Bit 0 is
reserved.
AMD Geode™ CS5535 Companion Device Data Book
Cycle Type
Intel FWH Read
Intel FWH Write
Memory Read
Memory Write
I/O Read
I/O Write
DMA Read
DMA Write
Bus Master Mem Read
Bus Master Mem Write
Bus Master I/O Read
Bus Master I/O Write
Table 5-22. Cycle Types Supported
LPC Protocol
1, 2, 4 Bytes
1, 2, 4 Bytes
1, 2, 4 Bytes
1, 2, 4 Bytes
1, 2, 4 Bytes
1, 2, 4 Bytes
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
1 Byte
Size
1 Byte Only
1 Byte Only
Supported
Size
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
SIZE: This field is one clock. It is driven by the host on
memory and DMA transfers to determine how many bytes
are to be transferred. Bits [1:0] are used to determine size
and bits [3:2] are reserved.
TAR: The Turn Around field is two clocks, and is driven by
the host when it is turning control over to a peripheral and
vice versa. In the first clock a host or a peripheral drives the
LAD[3:0] lines to 1111b, on the second cycle the host or
peripheral TRI-STATES the LAD[3:0] lines. These lines
have weak pull-ups so they will remain at a logical high
state.
ADDR: The Address field is four clocks for I/O cycles and
eight clocks for memory cycles. It is driven by the host on
target accesses. This field is not driven on DMA cycles.
The most significant nibble is driven first.
CHANNEL/Terminal Count: The Channel field is one
clock and driven by the host on DMA cycles to indicate the
DMA channel. Only 8-bit channels are supported (0, 1, 2,
3). DMA channel is communicated on LAD[2:0] and Termi-
nal Count (TC) is communicated through LAD3. TC indi-
cates the last byte of transfer, based upon the size of the
transfer. If an 8-bit transfer and TC is set, then this is the
last byte.
DATA: This field is two clocks, representing one byte data.
It is driven by the host on target and DMA cycles when data
is flowing to the peripheral, and by the peripheral when
data is flowing to the host. The lower nibble is driven first.
SYNC: This field can be several clocks in length and is
used to add wait states. Driven by the peripheral on target
or DMA cycles.
SYNC Timeout:
1)
2)
The host starts a cycle, but no device ever drives
SYNC valid. If the host observes three consecutive
clocks without a valid SYNC, it can abort the cycle.
The host starts a cycle, a device drives a SYNC valid
to insert wait states (LAD[3:0] = 0101b or 0110b), but
never completes it. This could happen if the peripheral
locks up for some reason. The peripheral should be
designed to prevent this case:
– If the SYNC pattern is 0101b, then the maximum
– If the SYNC pattern is 0110b, then no maximum
number of SYNC clocks is eight. If the host sees
more than eight, it may abort the cycle.
number of SYNC clocks took place, the peripheral
must have protection mechanisms to complete the
cycle.
31506B
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