CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 155

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Low Pin Count Port
AMD Geode™ CS5535 Companion Device Data Book
WSYNC
RSYNC
START
Signal
MSIZE
Number of Clock Cycles
IDSEL
ADDR
DATA
TAR
TAR
TAR
TAR
(FWH0-FWH3)
Clock
Cycle
LFRAME#
LAD[3:0]
1
1
7
1
1
1
2
1
2
1
1
(FWH4)
LCLK
LAD[3:0]
1101b
0000b
1111b
1111b
0101b
0000b
1111b
1111b
(float)
(float)
0000
xxxx
xxxx
START IDSEL
1
Peripheral
N/A
Figure 5-46. FWH Write Cycle
I/O
Table 5-27. FWH Read Cycle
O
O
O
O
O
I
I
I
I
I
1
ADDR
Description
On the rising edge of CLK with LFRAME# low, the contents of
LAD[3:0] indicate the start of an FWH cycle.
Indicates which FWH peripheral is selected. The value on the
LAD[3:0] is compared to the IDSEL strapping on the FWH device
pins to select which device is being addressed.
Note: From Intel 82802 Specification - the boot device must have
an ID (determined by ID strapping pins ID[3:0]) of 0. It is advisable
that subsequent devices use incremental numbering.
A 28-bit address phase is transferred starting with the most signifi-
cant nibble first.
Always 0000b (single byte transfer).
The LPC host drives LAD[3:0] to 1111b to indicate a turnaround
cycle.
The FWH device takes control of LAD[3:0] during this cycle.
The FWH device drives LAD[3:0] to 0101b (short wait-sync) for two
clock cycles, indicating that the data is not yet available.
The FWH device drives LAD[3:0] to 0000b, indicating that data will
be available during the next clock cycle.
Data transfer is two cycles, starting with least significant nibble.
The FWH device drives LAD[3:0] to 1111b, to indicate a turnaround
cycle.
The FWH device floats its output and the LPC host takes control of
LAD[3:0].
7
MSIZE
1
DATA
2
TAR
2
SYNC
31506B
1
TAR
2
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