CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 171
CS5535-UDCF
Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.CS5535-UDCF.pdf
(579 pages)
Specifications of CS5535-UDCF
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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CS5535-UDCF
Manufacturer:
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Multi-Function General Purpose Timer
Note 1. Compare 2 Value must be set to all 1s for pulse density modulation.
5.16.5
The Working power domain logic consists of the Local Bus
Interface, Control Logic, MSRs, and NMI, IRQ, and Reset
Output Events.
When Event mode is enabled, the NMI, IRQ, and Reset
Output Events logic gathers the event outputs of all eight
MFGPTs and then generates the interrupt and resets out-
puts based on MSR settings. The interrupt outputs go to
the PIC that can then trigger an IRQ or ASMI. Note that
MFGPT6 and MFGPT7 cannot trigger reset. These outputs
are controlled by MSR bits, and the NMI output can be fur-
ther controlled by the MSB of I/O Address 070h.
AMD Geode™ CS5535 Companion Device Data Book
Up Counter Output
Working Power Domain Logic
000
001
010
011
100
101
110
111
Table 5-33. MFGPT Pulse Density Modulation Example
Bit Reverse Output
000
100
010
110
001
101
011
111
Pulse Train Output for Given Compare 1 Value (Note 1)
1
0
1
1
1
1
1
1
1
5.16.6
The asynchronous internal Standby State signal will dis-
able/enable the Working power domain interface immedi-
ately. Therefore, any bus operation active at that time will
have an indeterminate result.
Power Domain Crossing Interface Logic
2
0
1
1
1
0
1
1
1
4
0
1
0
1
0
1
0
1
31506B
5
0
0
0
1
0
1
0
1
6
0
0
0
1
0
0
0
1
171
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