CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 187
CS5535-UDCF
Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.CS5535-UDCF.pdf
(579 pages)
Specifications of CS5535-UDCF
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
20 000
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Flash Controller
5.18.3
5.18.3.1 NOR/GPCS
The NOR/GPCS timing has two phases: address phase
and data phase.
In the address phase, the address bus and data bus
present a higher address, ADD[27:10]. Board designers
can use external latches, such as 74x373, to latch the
address bits.
In the data phase, the address bus presents ADD[9:0], and
the data bus is for data read or write.
The Flash Controller is running off internal Local bus clock,
which is at the highest frequency of 33 MHz. The address
phase is always two clock periods. The ALE signal asserts
high in the first-half clock period and de-asserts in the sec-
AMD Geode™ CS5535 Companion Device Data Book
ADD[9:0]
ALE
CS#
WE#, RE#
DATA (write)
DATA (read)
Flash Controller Interface Timing Diagrams
0
1
Higher Address
Higher Address
Higher Address
Address
Phase
2
Figure 5-57. NOR Flash Basic Timing
3
4
tS
tS
»
Lower Address
»
»
»
»
»
»
»
»
X
ond clock period. A 74LCX373 only needs 4 ns setup time
and 2 ns hold time (worst case). This timing provides a lot
of flexibility for the designing of the board. In the data
phase, the address bus and write data bus are available in
the first clock period. In the second clock period of the data
phase, chip select goes low. After the required hold time,
chip select goes high, and write data bus change. After one
Local bus clock from chip select change (going high),
address bus changes. The setup time, strobe pulse width,
and hold time are programmable through the NOR timing
registers. See Section 6.19.1.2 "NOR Flash Timing MSRs"
on page 522.
Figure 5-57 and Figure 5-58 provides some NOR Flash
timing examples.
»
»
»
»
»
»
»
Data Phase
Y
Data
tP
Y+1
Data
Y+2
31506B
»
»
»
»
»
»
»
»
tH
tH
Z
Z+1
Z+2
187
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