CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 193

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

TAP Controller
5.20
The TAP Controller is IEEE 1149.1 compliant. A block dia-
gram of the TAP, boundary scan and Internal scan is
shown in Figure 5-63. The JTAG pins TCK, TDI, TDO,
TMS, and RESET_STAND# are directly supported. The
TAP is programmable by means of TAP control instruc-
tions. The meanings of the various instructions are shown
in Table 5-38 on page 194 along with the length of the DR
(Data register) that can be accessed once the instruction is
entered. All Data registers shift in and out data LSB first.
The Instruction register and all Data registers are shift reg-
isters, so if more bits are shifted in than the register can
hold, only the last bits shifted in - the MSBs - will be used.
This can be useful on systems that always shift in a multi-
ple of 8 bits to the Data or Instruction registers. The
Instruction register is 24 bits wide and defined in Table 5-
39 on page 195.
The TAP Controller can be initialized synchronously or
asynchronously. For a synchronous reset, holding TMS
high and clocking TCK a minimum of five times will put the
TAP state machine into the Test-Logic-Reset state. Asyn-
chronous
RESET_STAND# (TAP Controller Reset) (see Section 4.6
"Reset
AMD Geode™ CS5535 Companion Device Data Book
RESET_STAND# or
LVD Standby Reset
TAP Controller
Considerations"
reset
TDO
TMS
TCK
is
Memory BIST Interface
TDI
available
Figure 5-63. TAP Controller, Boundary Scan Block Diagram
To Bscan
on
page
too
by
65).
asserting
To Iscan
From
Internal Scan Registers
Boundary Scan Registers
RESET_STAND#, the TAP state machine will immediately
enter the Test-Logic-Reset state.
The TAP has specific pre-assigned meanings to the bits in
the 24-bit IR register. The meanings are summarized in
Table 5-39. Note that the bits only affect the chip once the
“Update-IR” JTAG state occurs in the JTAG Controller -
shifting through these bits will not change the state of inter-
nal signals (e.g., test_mode). The details on JTAG Control-
ler states are covered in the IEEE 1149.1 standard.
Features
TAP control/access to the following:
• Shift/capture of CCU scan chain
• GLIU access via Request-in, Request-out packets
• TAPSCAN access
• TRI-STATE mode control
• Memory BIST control
• ID code
• Configures component for JTAG bypass mode
TAP
Serial Interface with GLCP
From Iscan
31506B
From Bscan
193