CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 200

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Universal Asynchronous Receiver-Transmitter (UART)
• Standard GeodeLink Device MSRs: Accessed via
• UART/IR Controller Specific MSRs: Accessed via
• UART/IR Controller Native Registers: Accessed via
Direct Memory Access (DMA)
• Standard GeodeLink Device MSRs: Accessed via
• DMA Specific MSRs: Accessed via RDMSR and
• DMA Native Registers: Accessed as I/O Addresses.
Low Pin Count (LPC)
• Standard GeodeLink Device MSRs: Accessed via
• LPC Specific MSRs: Accessed via RDMSR and
Real-Time Clock (RTC)
• Standard GeodeLink Device MSRs: Accessed via
• RTC Specific MSRs: Accessed via RDMSR and
• RTC Native Registers: Accessed as I/O addresses.
General Purpose Input Output (GPIO)
• Standard GeodeLink Device MSRs: Accessed via
• GPIO Native Registers: Accessed via a base address
Multi-Function General Purpose Timer (MFGPT)
• Standard GeodeLink Device MSRs: Accessed via
• MFGPT Specific MSRs: Accessed via RDMSR and
• MFGPT Native Registers: Accessed via a base address
Power Management Controller (PMC)
• Standard GeodeLink Device MSRs: Accessed via
• PMC Specific MSRs: Accessed via RDMSR and
200
RDMSR and WRMSR instructions. (Shared with DIVIL.)
RDMSR and WRMSR instructions.
Banks 0 through 7 as I/O offsets. See MSR_LEG_IO
(MSR 51400014h) bits [22:20] and bits [18:16] for
setting base address.
RDMSR and WRMSR instructions. (Shared with DIVIL.)
WRMSR instructions.
RDMSR and WRMSR instructions. (Shared with DIVIL.)
WRMSR instructions.
RDMSR and WRMSR instructions. (Shared with DIVIL.)
WRMSR instructions.
RDMSR and WRMSR instructions. (Shared with DIVIL.)
register, MSR_LBAR_GPIO (MSR 5140000Ch), as I/O
offsets.
— GPIO Low/High Bank Feature Bit Registers
— GPIO Input Conditioning Function Registers
— GPIO Interrupt and PME Registers
RDMSR and WRMSR instructions. (Shared with DIVIL.)
WRMSR instructions.
register, MSR_LBAR_MFGPT (MSR 5140000Dh), as
I/O offsets.
RDMSR and WRMSR instructions. (Shared with DIVIL.)
WRMSR instructions.
31506B
• ACPI Registers: Accessed via a base address register,
• PM Support Registers: Accessed via a base address
Flash Controller
• Standard GeodeLink Device MSRs: Accessed via
• Flash Controller Specific MSRs: Accessed via RDMSR
• Flash Controller Native Registers: Accessed via a base
GeodeLink Control Processor (GLCP)
• Standard GeodeLink™ Device (GLD) MSRs: Accessed
• GLCP Specific MSRs: Accessed via RDMSR and
Note that MSRs for the Floppy Port, PIT, PIC, KEL, SMB,
UART, DMA, LPC, RTC, GPIO, MFGPT, and Flash Con-
troller modules are part of the DIVIL (i.e., MSR 51400000h-
514000FFh). Hence, the Standard GeodeLink Device
MSRs (MSR 51400000h-51400007h) are documented in
the DIVIL register description and the device Specific
MSRs are documented in their appropriate register
description chapter.
The tables in this chapter use the following abbreviations:
Type
R/W
R
W
RO
WO
R/W1C
MSR_LBAR_ACPI (MSR 5140000Eh), as I/O offsets.
register, MSR_LBAR_PMS (MSR 5140000Fh), as I/O
offsets.
RDMSR and WRMSR instructions. (Shared with DIVIL.)
and WRMSR instructions.
address register as either memory or I/O offsets:
— MSR_LBAR_FLSH0 (MSR 51400010h) for use with
— MSR_LBAR_FLSH1 (MSR 51400011h) for use with
— MSR_LBAR_FLSH2 (MSR 51400012h) for use with
— MSR_LBAR_FLSH3 (MSR 51400013h) for use with
via RDMSR and WRMSR instructions.
WRMSR instructions.
FLASH_CS0#.
FLASH_CS1#.
FLASH_CS2#.
FLASH_CS3#.
AMD Geode™ CS5535 Companion Device Data Book
Description
Read/Write.
Read from a specific address returns the
value of a specific register.
Write to the same address is to a different
register.
Write.
Read Only.
Write Only.
Read/Write 1 to clear. Writing 1 to a bit
clears it to 0. Writing 0 has no effect.
Register Descriptions