CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 221

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ Interface Unit Register Descriptions
6.1.3.15 Request Compare Value (GLIU_RQ_COMP_VAL)
MSR Address
Type
Reset Value
The RQ Compare Value and the RQ Compare Mask enable traps on specific transactions. A hit to the RQ Compare is
determined by hit = (RQ_IN & RQ_COMP_MASK) == RQ_COMP_VAL). A hit can trigger the RQ_COMP error sources
when they are enabled. The value is compared only after the packet is arbitrated.
AMD Geode™ CS5535 Companion Device Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:53
52:0
Bit
Bit
3
2
1
0
Name
HIT_ERR
HIT_SMI
HIT_DEC
HIT_LDEN
Name
RSVD
RQ_COMPVAL
RSVD
510100C0h
R/W
001FFFFF_FFFFFFFFh
GLIU_STATISTIC_ACTION[x] Bit Descriptions (Continued)
Description
Assert AERR on Descriptor Hit. This bit causes an asynchronous error to be generated
when a matching descriptor hit occurs, or not. The descriptor hits are ANDed with the
masks and then all ORed together.
0: Disable.
1: Enable.
Assert ASMI on Descriptor Hit. This bit causes an ASMI to be generated when a
matching descriptor hit occurs, or not. The descriptor hits are ANDed with the masks and
then all ORed together.
0: Disable.
1: Enable.
Decrement Counter on Descriptor Hit. This bit causes the associated counter to dec-
rement when a matching descriptor hit occurs, or not.The descriptor hits are ANDed with
the masks and then all ORed together.
0: Disable.
1: Enable.
Load Counter on Descriptor Hit. This bit causes the associated counter to reload its
LOAD_VAL when a matching descriptor hit occurs, or not.The descriptor hits are ANDed
with the masks and then all ORed together.
0: Disable.
1: Enable.
Description
Reserved. Write as read.
Request Packet Value. This is the value compared against the logical bit-wise AND of
the incoming request packet and the RQ_COMP_MASK in order to determine a hit.
GLIU_RQ_COMP_VAL Bit Descriptions
GLIU_RQ_COMP_VAL Register Map
RQ_COMPVAL
RQ_COMPVAL
9
8
31506B
7
6
5
4
3
2
1
221
0