CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 231

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ PCI South Bridge Register Descriptions
6.2.1.3
MSR Address
Type
Reset Value
The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns
the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.8.3 "MSR Address 2: SMI Control" on page 74 for
further SMI/ASMI generation details.)
AMD Geode™ CS5535 Companion Device Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:23
15:7
Bit
22
21
20
19
18
17
16
6
5
4
GLD SMI MSR (GLPCI_GLD_MSR_SMI)
Name
RSVD (RO)
TAS_ASMI_
FLAG
PAR_ASMI_
FLAG
SYSE_ASMI_
FLAG
EXCEP_ASMI_
FLAG
SSMI_ASMI_
FLAG
TAR_ASMI_
FLAG
MAR_ASMI_
FLAG
RSVD (RO)
TAS_ASMI_EN
PAR_ASMI_EN
SYSE_ASMI_
EN
RSVD
51000002h
R/W
00000000_00000000h
Description
Reserved (Read Only). Returns 0.
Target Abort Signaled ASMI Flag. If high, records that an ASMI was generated due the
signaling of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
TA_ASMI_EN (bit 6) must be high to generate ASMI and set flag.
Parity Error ASMI Flag. If high, records that an ASMI was generated due to the detec-
tion of a PCI bus parity error. Write 1 to clear; writing 0 has no effect. PAR_ASMI_EN (bit
5) must be high to generate ASMI and set flag.
System Error ASMI Flag. If high, records that an ASMI was generated due to the detec-
tion of a PCI bus system error. Write 1 to clear; writing 0 has no effect. SYSE_ASMI_EN
(bit 4) must be high to generate ASMI and set flag.
Exception Bit Flag. If high, records that an ASMI was generated due to the EXCEP bit
being set in the received GLIU read or write response packet. Write 1 to clear; writing 0
has no effect. EXCEP_ASMI_EN (bit 3) must be set to enable this flag.
SSMI ASMI Flag. If high, records that an ASMI was generated due to the SSMI bit being
set in the received GLIU read or write response packet. Write 1 to clear; writing 0 has no
effect. SSMI_ASMI_EN (bit 2) must be set to enable this flag.
Target Abort Received ASMI Flag. If high, records that an ASMI was generated due to
the reception of a target abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
TAR_ASMI_EN (bit 1) must be high to generate ASMI and set flag.
Master Abort Received ASMI Flag. If high, records that an ASMI was generated due to
the reception of a master abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
MAR_ASMI_EN (bit 0) be high to generate ASMI and set flag.
Reserved (Read Only). Returns 0.
Target Abort Signaled ASMI Enable. Write 1 to enable TAS_ASMI_FLAG (bit 22) and
to allow the event to generate an ASMI.
Parity Error ASMI Enable. Write 1 to enable PAR_ASMI_FLAG (bit 21) and to allow the
event to generate an ASMI.
System Error SMI Enable. Write 1 to enable SYSE_ASMI_FLAG (bit 20) and to allow
the event to generate an ASMI.
GLPCI_GLD_MSR_SMI Bit Descriptions
GLPCI_GLD_MSR_SMI Register Map
RSVD
RSVD
9
8
31506B
7
6
5
4
3
2
1
231
0