CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 235

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ PCI South Bridge Register Descriptions
AMD Geode™ CS5535 Companion Device Data Book
63:60
59:56
55:52
51:49
48:43
41:40
39:35
34:32
31:24
23:21
Bit
42
20
Name
FTH
RTH
RSVD
(RO)
RTL
RSVD
(RO)
SLTO
ILTO
LAT
0
(RO)
RSVD
(RO)
SUS
RSVD
(RO)
IB/OB
IB/OB
IB/OB
IB/OB
OB
IB
IB
---
---
IB
IB
---
---
Description
In-Bound Flush Threshold. Controls the timing for requesting new read data while
concurrently flushing previously prefetched, stale read data. While flushing stale data, if
the number of prefetched 64-bit WORDs reaches this level, then a new read request is
made.
In-Bound Read Threshold. Controls the timing for prefetching read data. If the number
of prefetched 32-bit WORDs is decremented and reaches this threshold, a subsequent
GLIU request is generated to fetch the next cache-line of read data.
Reserved (Read Only). Returns 0.
Retry Transaction Limit. Limits the number of out-bound retries. If a target signals retry
indefinitely the PCI interface may be configured to abort the failing out-bound request.
000: No limit.
001: 8 retries.
010: 16 retries.
011: 32 retries.
Reserved (Read Only). Returns 0.
Subsequent Latency Time-Out Select. Specifies the subsequent target latency time-
out limit. If, within a burst, the GLPCI_SB module does not respond with the configured
number of clock edges the PCI interface terminates the PCI bus cycle.
0: 8 PCI clock edges.
1: 4 PCI clock edges.
Initial Latency Time-out Select. Specifies the initial target latency time-out limit for the
PCI interface. If the GLPCI_SB module does not respond with the first data phase within
the configured number of clock edges the PCI interface terminates the PCI bus cycle.
00: 32 PCI clock edges.
01: 16 PCI clock edges.
PCI Usage Timer. Usage time-out value for limiting bus tenure.
Constant 0 (Read Only). The three least significant bits of the PCI latency timer field
are fixed as zeros. These bits are not used as part of the PCI latency timer comparison.
Reserved (Read Only). Returns 0.
Busy Sustain. Controls the sustain time for keeping the clocks running after the internal
busy signals indicate that the clocks may be gated.
000: No sustain.
001: 4 clock cycles.
010: 8 clock cycles.
011: 16 clock cycles.
Reserved (Read Only). Returns 0.
GLPCI_CTRL Bit Descriptions
100: 64 retries.
101: 128 retries.
110: 256 retries.
111: 512 retries.
10: 8 PCI clock edges.
11: 4 PCI clock edges.
100: 32 clock cycles.
101: 64 clock cycles.
110: 128 clock cycles.
111: 256 clock cycles.
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