CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 245

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AC97 Audio Codec Controller Register Descriptions
6.3
The control registers for the AC97 Audio Codec Controller
(ACC) are divided into two register sets:
• Standard GeodeLink™ Device (GLD) MSRs
• ACC Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 4.2 "MSR
Addressing" on page 59 for more details.
The ACC Native registers begin at ACC Offset 00h. The
system automatically maps the ACC registers to a location
in memory space or I/O space, but this is hidden from the
module’s point of view. At the audio block level, it does not
matter if these registers are in memory or I/O space but at
the system level, there are significant operational differ-
ences (see Section "Eliminating Race Conditions") Hereaf-
ter the ACC Address are called out as I/O Offsets, since
I/O mapping is recommended.
For Native register access, only the lower seven bits of the
address are decoded, so the register space is aliased.
Accesses beyond 7Fh alias below 7Fh. Accesses to
addresses that are not implemented or reserved are “don’t
cares” (i.e. writes do nothing, reads return 0s).
Tables 6-8 and 6-9 are ACC register summary tables that
include reset values and page references where the bit
descriptions are provided.
AMD Geode™ CS5535 Companion Device Data Book
MSR Address
51500000h
51500001h
51500002h
51500003h
51500004h
51500005h
AC97 Audio Codec Controller Register Descriptions
Type
R/W
R/W
R/W
R/W
R/W
RO
Table 6-8. Standard GeodeLink™ Device MSRs Summary
Register Name
GLD Capabilities MSR (ACC_GLD_MSR_CAP)
GLD Master Configuration MSR
(ACC_GLD_MSR_CONFIG)
GLD SMI MSR (ACC_GLD_MSR_SMI)
GLD Error MSR (ACC_GLD_MSR_ERROR)
GLD Power Management MSR
(ACC_GLD_MSR_PM)
GLD Diagnostic MSR (ACC_GLD_MSR_DIAG)
Eliminating Race Conditions
All I/O writes are sequence locked, that is, completion of
the write at the target is confirmed before the executing
processor proceeds to the next instruction. All memory
writes are posted, that is, the executing processor pro-
ceeds to the next instruction immediately after the write
whether or not the write has completed. Write posting can
lead to out of order execution. Reading the register to
which a write has been posted, forces any pending posted
write to execute if it has not already done so.
Consider this example. Assume an audio master is per-
forming an access to system memory and register access
is temporarily blocked. If the processor was servicing an
interrupt, a write to clear the interrupt would post to a mem-
ory mapped register but not execute immediately, that is,
the interrupt would not immediately clear. If the processor
then enabled the Programmable Interrupt Controller (PIC)
for new interrupts, then the “not immediately cleared” inter-
rupt would cause a false new interrupt, a form of a race
condition.
This type of race condition can be eliminated by placing the
audio registers in I/O space, or, by performing a register
read to any register having a pending posted write that is
capable of creating a race condition.
00000000_0000F000h
00000000_00000000h
00000000_00000000h
00000000_00000000h
00000000_002330xxh
00000000_00000000h
Reset Value
31506B
Reference
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