CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 250

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
20 000
6.3.1.4
MSR Address
Type
Reset Value
The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns
the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.8.3 "MSR Address 2: SMI Control" on page 74 for
further details.)
250
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:33
31:1
Bit
32
0
GLD Error MSR (ACC_GLD_MSR_ERROR)
Name
RSVD
IRQ_SSMI_FLAG
RSVD
IRQ_SSMI_EN
51500003h
R/W
00000000_00000000h
31506B
Description
Reserved. Reads return 0.
IRQ SSMI Flag. If high, records that an SSMI was generated because the ACC inter-
rupt signal transitioned from 0 to 1. This bit is unaffected when the interrupt transitions
from 1 to 0. Write 1 to clear; writing 0 has no effect. IRQ_SSMI_EN (bit 1) must be set
to enable this event and set flag.
Reserved. Reads return 0.
IRQ SSMI Enable. Write 1 to enable IRQ_SSMI_FLAG (bit 32) and to allow the event
to generate an SSMI.
ACC_GLD_MSR_ERROR Register Map
ACC_GLD_MSR_SMI Bit Descriptions
RSVD
RSVD
AMD Geode™ CS5535 Companion Device Data Book
AC97 Audio Codec Controller Register Descriptions
9
8
7
6
5
4
3
2
1
0

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