CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 256

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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6.3.2.5
ACC I/O Offset
Type
Reset Value
256
15:10
15
15:0
Bit
Bit
16
9
8
7
6
5
Second Level Audio IRQ Status Register (ACC_IRQ_STATUS)
14
Name
CMD_NEW
CMD_DATA
Name
RSVD
BM7_IRQ_STS
BM6_IRQ_STS
BM5_IRQ_STS
BM4_IRQ_STS
BM3_IRQ_STS
13
12h
RO
00000000h
RSVD
31506B
12
ACC_CODEC_CNTL Bit Descriptions (Continued)
11
Description
Codec Command New. Indicates if the codec command in bits [31:22] (and [15:0] for
writes) is new.
0: Not new.
1: New.
This bit is to be set by software when a new command is loaded. It is cleared by hard-
ware when the command is sent to the codec. Software must wait for this bit to clear
before loading another command.
This bit can not be cleared by software. When the CODEC_CNTL register is written by
software with bit 16 cleared, then bits [31:22] and [15:0] are unaffected. Thus, bit 16 is
an "enable" allowing bits [31:22] and [15:0] to be changed.
Codec Command Data. This is the command data being sent to the codec in slot 2,
bits [19:12] of the serial output stream. This is used for writing data into one of the reg-
isters in the AC97 codec. The contents are only sent to the codec for write commands
(bit [31] = 0). For reads slot 2, bits[19:12] are stuffed with 0s.
Description
Reserved. Reads return 0.
Audio Bus Master 7 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 7. Reading the Bus Master 7 IRQ Status
Register clears this bit.
Audio Bus Master 6 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 6. Reading the Bus Master 6 IRQ Status
Register clears this bit.
Audio Bus Master 5 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 5. Reading the Bus Master 5 IRQ Status
Register clears this bit.
Audio Bus Master 4 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 4. Reading the Bus Master 4 IRQ Status
Register clears this bit.
Audio Bus Master 3 IRQ Status. If this bit is set, it indicates that an IRQ was caused
by an event occurring on Audio Bus Master 3. Reading the Bus Master 3 IRQ Status
Register clears this bit.
ACC_IRQ_STATUS Bit Descriptions
10
ACC_IRQ_STATUS Register Map
9
8
7
AMD Geode™ CS5535 Companion Device Data Book
6
AC97 Audio Codec Controller Register Descriptions
5
4
3
2
1
0

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