CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 259

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

AC97 Audio Codec Controller Register Descriptions
6.3.2.8
Bus Master 0 IRQ Status (ACC_BM0_STATUS)
ACC I/O Offset
Type
Reset Value
Bus Master 1 IRQ Status (ACC_BM1_STATUS)
ACC I/O Offset
Type
Reset Value
Bus Master 2 IRQ Status (ACC_BM2_STATUS)
ACC I/O Offset
Type
Reset Value
Bus Master 3 IRQ Status (ACC_BM3_STATUS)
ACC I/O Offset
Type
Reset Value
AMD Geode™ CS5535 Companion Device Data Book
Bit
7:2
1
0
7
Audio Bus Master 0-7 IRQ Status Registers (ACC_BM[x]_STATUS)
Name
RSVD
BM_EOP_ERR
EOP
21h
RC
00h
29h
RC
00h
31h
RC
00h
39h
RC
00h
6
Description
Reserved. Reads return 0
Bus Master Error. If this bit is set, it indicates that hardware encountered a second
EOP before software cleared the first EOP.
If hardware encounters a second EOP (end of page) before software clears the first
EOP, it causes the bus master to pause until this register is read to clear the error. Read
to clear.
End of Page. If this bit is set, it indicates the bus master transferred data that is marked
by the EOP bit in the PRD table (bit 30). Read to clear.
5
ACC_BM[x]_STATUS Bit Descriptions
ACC_BM[x]_STATUS Register Map
RSVD
4
Bus Master 4 IRQ Status (ACC_BM4_STATUS)
ACC I/O Offset
Type
Reset Value
Bus Master 5 IRQ Status (ACC_BM5_STATUS)
ACC I/O Offset
Type
Reset Value
Bus Master 6 IRQ Status (ACC_BM6_STATUS)
ACC I/O Offset
Type
Reset Value
Bus Master 7 IRQ Status (ACC_BM7_STATUS)
ACC I/O Offset
Type
Reset Value
3
41h
RC
00h
49h
RC
00h
51h
RC
00h
59h
RC
00h
2
31506B
BM_EOP_ERR
1
EOP
0
259