CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 265

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ATA-5 Controller Register Descriptions
6.4.1.3
MSR Address
Type
Reset Value
The flags are set by internal conditions. The internal conditions are enabled if the EN bit is 1. Reading the FLAG bit returns
the value; writing 1 clears the flag; writing 0 has no effect. (See Section 4.8.3 "MSR Address 2: SMI Control" on page 74 for
further details.)
AMD Geode™ CS5535 Companion Device Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:34
31:2
Bit
2:0
Bit
33
32
3
1
0
GLD SMI MSR (ATAC_GLD_MSR_SMI)
Name
RSVD (RO)
PID
Name
RSVD
IDE_CH0_IRQ_
ASMI_FLAG
IDE_PIO_SSMI
FLAG
RSVD
IDE_CH0_IRQ_
ASMI_EN
IDE_PIO_SSMI
EN
51300002h
R/W
00000000_00000000h
ATAC_GLD_MSR_CONFIG Bit Descriptions (Continued)
Description
Reserved (Read Only). Returns 0.
Priority ID. Always write 0.
Description
Reserved. Read returns 0.
IDE Channel 0 IRQ ASMI Flag. If high, records that an ASMI was generated due to an
IRQ event. Write 1 to clear; writing 0 has no effect. IDE_CH0_IRQ_ASMI_EN (bit 1)
must be set to enable this event and set flag.
IDE Programmable I/O SSMI Flag. If high, records that an SSMI was generated due
to a PIO transaction occurring during a DMA command. Write 1 to clear; writing 0 has
no effect. IDE_PIO_SMI_EN (bit 0) must be set to enable this event and set flag.
Reserved. Read returns 0.
IDE Channel 0 IRQ ASMI Mask. Write 1 to enable IDE_CH0_IRQ_ASMI_FLAG (bit
33) and to allow the event to generate an ASMI.
IDE Programmable I/O SSMI Mask. Write 1 to enable IDE_PIO_SSMI_FLAG (bit 32)
and to allow the event to generate an SSMI.
ATAC_GLD_MSR_SMI Bit Descriptions
ATAC_GLD_MSR_SMI Register Map
RSVD
RSVD
9
8
31506B
7
6
5
4
3
2
1
265
0