CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 272

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

272
If bit 20 = 0, Multi-word DMA.
If bit 20 = 1, Ultra DMA.
Note: Register settings described as “Value + n cycle(s)” produce timings for the indicated parameter as measured in
63:32
30:24
23:21
19:16
15:12
30:24
23:21
19:16
15:12
11:8
11:8
Bit
7:4
3:0
7:4
3:0
31
20
31
20
66 MHz clock cycles. The ‘value’ that is entered is the desired number of 66 MHz clock cycles in hexadecimal;
the actual parameter timing generated by that entry is the entered ‘value’ plus the indicated number of ‘cycles’
(‘n’) as listed in the description of that parameter.
Name
RSVD
PIO_FORM
MODE66_SEL
RSVD
DMA_SEL
tKR
tDR
tKW
tDW
tM
PIO_FORM
MODE66_SEL
RSVD
DMA_SEL
tCRC
tSS
tCYC
tRP
tACK
31506B
Description
Reserved. Set to 0.
PIO Mode Format.
0: Format 0.
1: Format 1.
Mode 66 Select: Set to 7Fh for 66 MHz system clock.
Reserved. Set to 0.
DMA Select. DMA operation.
0: Multi-word DMA.
1: Ultra DMA.
IDE_IOR# Recovery Time (4-bit). Value + 1 cycle.
IDE_IOR# Pulse Width. Value + 1 cycle.
IDE_IOW# Recovery Time (4-bit). Value + 1 cycle.
IDE_IOW# Pulse Width. Value + 1 cycle.
IDE_CS0#/CS1# to IDE_IOR#/IOW# Setup; IDE_CS0#/CS1# Setup to
IDE_DACK0#/DACK1#.
PIO Mode Format.
0: Format 0.
1: Format 1.
Mode 66 Select: Set to 7Fh for 66 MHz system clock.
Reserved. Set to 011. Will read back as 011.
DMA Select. DMA operation.
0: Multi-word DMA.
1: Ultra DMA.
CRC Setup UDMA in IDE_DACK#. Value + 1 cycle (for host terminate CRC setup =
tMLI + tSS).
UDMA Out. Value + 1 cycle.
Data Setup and Cycle Time UDMA Out. Value + 2 cycles.
Ready to Pause Time. Value + 1 cycle. Used only for UDMA-in.
Note:
IDE_CS0#/CS1# Setup to IDE_DACK0#/DACK1#. Value + 1 cycle.
Settings for:
Settings for:
ATAC_CH0D0_DMA Bit Descriptions
tRFS + 1 tRP on next clock.
Multi-word DMA Mode 0 = 7F0FFFF3h
Multi-word DMA Mode 1 = 7F035352h
Multi-word DMA Mode 2 = 7F024241h
Ultra DMA Mode 0 = 7F7436A1h
Ultra DMA Mode 1 = 7F733481h
Ultra DMA Mode 2 = 7F723261h
Ultra DMA Mode 3 = 7F713161h
Ultra DMA Mode 4 = 7F703061h
AMD Geode™ CS5535 Companion Device Data Book
ATA-5 Controller Register Descriptions