CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 322

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

322
39:38
31:17
Bit
46
45
44
43
42
41
40
37
36
35
34
33
32
16
15
14
13
Name
NAND_DIST_
ERR_FLAG
RSVD
DMA_DMA_
ERR_FLAG
LPC_DMA_
ERR_FLAG
RSVD
UART2_DMA_
ERR_FLAG
UART1_DMA_
ERR_FLAG
RSVD
LPC_MAST_
ERR_FLAG
LPC_SLV_
ERR_FLAG
MAST_RESP_
EXCEP_FLAG
REPEAT_SSMI_
ERR_FLAG
DECODE_ERR_
FLAG
LB_ADAP_BAD_
FLAG
RSVD
LPC_EXCP_EN
SHTDWN_
ERR_EN
NAND_DIST_
ERR_EN
RSVD
31506B
DIVIL_GLD_MSR_ERROR Bit Descriptions (Continued)
Description
NAND Distract Error Flag. If high, records that an ERR was generated due to a NAND
distract error. NAND_DIST_ERR_EN (bit 14) must be high to generate ERR and set
flag. Write 1 to clear; writing 0 has no effect.
Reserved. Reads return 0. Writes have no effect.
8237 DMA Error Flag. If high, records that an ERR was generated due to an access
on the 8237s during DMA. DMA_DMA_ERR_EN (bit 12) must be high to generate ERR
and set flag. Write 1 to clear; writing 0 has no effect.
LPC DMA Error Flag. If high, records that an ERR was generated due to an LPC
access during DMA. LPC_DMA_ERR_EN (bit 11) must be high to generate ERR and
set flag. Write 1 to clear; writing 0 has no effect.
Reserved. Reads return 0. Writes have no effect.
UART2 DMA Error Flag. If high, records that an ERR was generated due to a UART2
access during DMA. UART2_DMA_ERR_EN (bit 9) must be high to generate ERR and
set flag. Write 1 to clear; writing 0 has no effect.
UART1 DMA Error Flag. If high, records that an ERR was generated due to a UART1
access during DMA. UART1_DMA_ERR_EN (bit 8) must be high to generate ERR and
set flag. Write 1 to clear; writing 0 has no effect.
Reserved. Reads return 0. Writes have no effect.
LPC Master Error Flag. If high, records that an ERR was generated on the LPC due to
a Master <=> GeodeLink Adapter transaction. LPC_MAST_ERR_EN (bit 5) must be
high to generate ERR and set flag. Write 1 to clear; writing 0 has no effect.
LPC Slave Error Flag. If high, records that an ERR was generated on the LPC due to
a Slave <=> GeodeLink Adapter transaction. LPC_SLV_ERR_EN (bit 4) must be high
to generate ERR and set flag. Write 1 to clear; writing 0 has no effect.
Master Response Exception Flag. If high, records that an ERR was generated due to
the GeodeLink Adapter detecting the EXCEP bit set in a local bus master response
packet. MAST_RESP_EXCP_EN (bit 3) must be high to generate ERR and set flag.
Write 1 to clear; writing 0 has no effect.
Repeat SSMI Error Flag. If high, records that an ERR was generated due to a second
SSMI occurring on an address before the first was cleared. REPEAT_SSMI_ERR_EN
(bit 2) must be high to generate ERR and set flag. Write 1 to clear; writing 0 has no
effect.
Decode Error Flag. If high, records that an ERR was generated during the address
decode cycle due to one or more devices being decoded to the same address. Bits
[54:52] record further information about this type of error. DECODE_ERR_EN (bit 1)
must be high to generate ERR and set flag. Write 1 to clear; writing 0 has no effect.
LBus Adapter Bad Flag. If high, records that an ERR was generated due to the
GeodeLink Adapter detected an error at the GeodeLink interface (e.g., packet type not
supported). LB_ADAP_BAD_EN (bit 0) must be high to generate ERR and set flag.
Write 1 to clear; writing 0 has no effect.
Reserved. Reads return 0. Writes have no effect.
LPC Exception Enable. Write 1 to enable EXCEP bit in response packet for LPC
address errors.
Shutdown Error Enable. Write 1 to enable SHTDWN_ERR_FLAG (bit 47) and to
allow a Shutdown cycle to generate an ERR.
NAND Distract Error Enable. Write 1 to enable NAND_DIST_ERR_FLAG (bit 46) and
to allow a NAND distract error to generate an ERR.
Reserved. Reads return 0. Writes have no effect.
AMD Geode™ CS5535 Companion Device Data Book
Diverse Integration Logic Register Descriptions