CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 326

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.2.2
MSR Address
Type
Reset Value
See Section 5.6.1 "LBARs and Comparators" on page 105 for operational details.
The KEL registers take 4 KB of memory space. However, only offsets 100h, 104h, 108h, and 10Ch contain registers. All
other writes are “don’t care” and reads return 0.
This is one of two KEL LBARs. Each LBAR “hits” to the same KEL. This allows USB Host Controllers at different addresses
to be used, if desired. Both LBARs do NOT have to be used.
6.6.2.3
MSR Address
Type
Reset Value
See Section 5.6.1 "LBARs and Comparators" on page 105 for operational details.
The KEL registers take 4 KB of memory space. However, only offsets 100h, 104h, 108h, and 10Ch contain registers. All
other writes are “don’t care” and reads return 0.
This is one of two KEL LBARs. Each LBAR "hits" to the same KEL. This allows USB Host Controllers at different addresses
to be used if desired. Both LBARs do NOT have to be used.
326
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:44
43:33
31:12
11:0
Bit
32
Local BAR - KEL from USB Host Controller 1 (DIVIL_LBAR_KEL1)
Local BAR - KEL from USB Host Controller 2 (DIVIL_LBAR_KEL2)
Name
MEM_MASK
RSVD
LBAR_EN
BASE_ADDR
RSVD
51400009h
R/W
00000000_00000000h
5140000Ah
R/W
00000000_00000000h
31506B
BASE_ADDR
BASE_ADDR
MEM_MASK
MEM_MASK
Description
Memory Address Mask Value. See discussion in Section 5.6.1 "LBARs and Compar-
ators" on page 105
Reserved. Reads return 0; writes have no effect.
LBAR Enable.
0: Disable LBAR.
1: Enable LBAR.
Base Address in Memory Space. See discussion in Section 5.6.1 "LBARs and Com-
parators" on page 105
Reserved. Reads return 0; writes have no effect.
DIVIL_LBAR_KEL1 Bit Descriptions
DIVIL_LBAR_KEL1 Register Map
DIVIL_LBAR_KEL2 Register Map
AMD Geode™ CS5535 Companion Device Data Book
Diverse Integration Logic Register Descriptions
9
9
8
8
7
7
RSVD
RSVD
RSVD
RSVD
6
6
5
5
4
4
3
3
2
2
1
1
0
0