CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 332

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.2.9
See Section 5.6.1 "LBARs and Comparators" on page 105
for operational details.
The NAND Flash control registers take 16 bytes of I/O
space. NOR Flash maps into some multiple of 4k bytes.
There are two forms of this LBAR depending on the space,
memory or I/O, Flash Device 0 is mapped into. Space is
determined by bit 34 of the LBAR.
Local BAR - Flash Chip Select 0 (DIVIL_LBAR_FLSH0)
MSR Address
Type
Reset Value
Uses FLASH_CS0# and FLASH_CE0#.
332
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
If bit 34 = 0; I/O Mapped
63:49
47:36
Bit
48
35
34
33
Local BAR - Flash Chip Select (DIVIL_LBAR_FLSH[x])
Name
RSVD
RSVD
IO_MASK
RSVD
MEM_IO
NOR_NAND
51400010h
R/W
00000000_00000000h
31506B
RSVD
RSVD
BASE_ADDR
MEM_MASK
Description
Reserved. Reads return value written. Defaults to 0
Reserved. Always write 0.
I/O Address Mask Value. For standard NAND Flash, bits [48:36] should be set to all
1s. Add 0s from the LSBs as needed for OEM specific devices that take more than 16
bytes.See discussion in Section 5.6.1 "LBARs and Comparators" on page 105
Reserved. Reads return value written. Defaults to 0.
Memory or I/O Mapped.
0: LBAR is I/O mapped).
1: LBAR is memory mapped.
NOR or NAND.
0: Use NOR chip select (FLASH_CS[x]#).
1: Use NAND chip select (FLASH_CE[x]#).
DIVIL_LBAR_FLSH[x] Bit Descriptions
DIVIL_LBAR_FLSH[x] Register Map
Local BAR - Flash Chip Select 1 (DIVIL_LBAR_FLSH1)
MSR Address
Type
Reset Value
Uses FLASH_CS1# and FLASH_CE1#.
Local BAR - Flash Chip Select 2 (DIVIL_LBAR_FLSH2)
MSR Address
Type
Reset Value
Uses FLASH_CS2# and FLASH_CE2#.
Local BAR - Flash Chip Select 3 (DIVIL_LBAR_FLSH3)
MSR Address
Type
Reset Value
Uses FLASH_CS3# and FLASH_CE3#.
AMD Geode™ CS5535 Companion Device Data Book
Diverse Integration Logic Register Descriptions
BASE_ADDR
IO_MASK
51400011h
R/W
00000000_00000000h
51400012h
R/W
00000000_00000000h
51400013h
R/W
00000000_00000000h
9
8
RSVD
7
RSVD
6
5
4
3
RSVD
0
1
2
1
0