CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 336

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

336
31:12
11:10
Bit
9:8
3:2
7
6
5
4
1
0
Name
RSVD
SEC_BOOT_LOC
BOOT_OP_
LATCHED (RO)
RSVD
PIN_OPT_LALL
PIN_OPT_LIRQ
PIN_OPT_LDRQ
PRI_BOOT_LOC
[1:0]
RSVD
PIN_OPT_IDE
31506B
Description
Reserved. Reads always return 0. Writes have no effect; by convention, always write
0.
Secondary Boot Location. Determines which chip select asserts for addresses in the
range F00F0000h to F00F3FFFh. Defaults to the same value as boot option:
00: LPC ROM.
01: Reserved.
10: Flash.
11: FirmWare Hub.
Latched Value of Boot Option (Read Only). For values, see Table 3-5 "Boot Options
Selection" on page 34.
Reserved. Reads return value written. By convention, always write 0. Defaults low.
All LPC Pin Option Selection.
0: All LPC pins become GPIOs including LPC_DRQ# and LPC_SERIRQ.
1: All LPC pins are controlled by the LPC controller except LPC_DRQ# and
When this bit is low, there is an implied high for the LPC_DISABLE_MEM and
LPC_DISABLE_IO bits in DIVIL_LEG_IO (DIVIL MSR 51400014h[25:24]).
LPC_SERIRQ or GPIO21 Pin Option Selection.
0: Ball G2 is GPIO21.
1: Ball G2 functions as LPC_SERIRQ. (Default)
LPC_DRQ# or GPIO20 Pin Option Selection.
0: Ball G1 is GPIO20.
1: Ball G2 functions as LPC_DRQ#. (Default)
Primary Boot Location. Determines which chip select asserts for addresses at or
above F0000000h, except those in the range specified by SEC_BOOT_LOC (bits
[11:10]). Defaults to the same value as boot option.
00: LPC ROM.
01: Reserved.
10: Flash.
11: FirmWare Hub.
Reserved. Reads return value written. By convention, always write 0. Defaults low.
IDE or Flash Controller Pin Function Selection.
0: All IDE pins associated with Flash Controller. Default if BOS[1:0] = 10.
1: All IDE pins associated with IDE Controller. Default if BOS[1:0] = 00 or 11.
IDE_IRQ0 is multiplexed with GPIO2; therefore, this bit has no affect with regards to
programming IDE_IRQ0. See Table 3-5 "Boot Options Selection" on page 34 for
BOS[1:0] programming values.
Ball H3 functions as GPIO22
Ball H2 functions as GPIO16
Ball J2 functions as GPIO17
Ball J1 functions as GPIO18
Ball K1 functions as GPIO19
Ball G1 functions as GPIO20
Ball G2 functions as GPIO21
LPC_SERIRQ use are determined by bits [5:4]. (Default)
Ball H3 functions as LPC_FRAME#
Ball H2 functions as LPC_AD0
Ball J2 functions as LPC_AD1
Ball J1 functions as LPC_AD2
Ball K1 functions as LPC_AD3
DIVIL_BALL_OPTS Bit Descriptions
AMD Geode™ CS5535 Companion Device Data Book
Diverse Integration Logic Register Descriptions