CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 338

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.6.2.14 Access Control DMA Request (DIVIL_AC_DMA)
MSR Address
Type
Reset Value
The controls below only affect memory and I/O accesses to the target slaves. MSR accesses are not affected. However,
MSR writes during DMA may have unintended side effects.
Note that when in demand or block mode, the UART reads and writes are disallowed; no corresponding mechanism exists
to allow UART controller reads or writes during UART activity. If attempted, CPU writes have no effect and the CPU reads
return all 1s.
The enables default to 0. If 0, reads or writes to the indicated device are blocked during activity. This may cause an SSMI
or ERROR if enabled by the associated MSR. Thus, writes are discarded and reads return all Fs. If an enable is 0, a chip
select for the indicated device is not asserted. If an enable is 1, the indicated device is available for access during activity.
338
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:18
15:4
Bit
17
16
3
2
1
0
Name
RSVD
AC_DMA_W
AC_DMA_R
RSVD
AC_DMA_LPC_
IW
AC_DMA_LPC_IR
AC_DMA_LPC_
MW
AC_DMA_LPC_
MR
5140001Eh
R/W
00000000h
31506B
RSVD
Description
Reserved. Reads return 0; writes have no effect.
Allow DMA Writes during DMA Activity. If set, this bit allows writes to the DMA con-
troller during DMA activity (data transfers). This mechanism may be used, among other
things, to abort a hung DMA transfer. If clear, DMA controller writes are locked out dur-
ing DMA activity.
Allow DMA Reads during DMA Activity. If set, this bit allows reads from the DMA
controller during DMA activity (data transfers). If clear, DMA controller reads are locked
out during DMA activity.
Reserved. Reads return 0; writes have no effect.
LPC I/O Writes during LPC DMA If set, this bit allows I/O writes to the LPC bus during
LPC DMA transfer. If clear, I/O writes are locked out during LPC DMA transfers.
LPC I/O Reads during LPC DMA. If set, this bit allows I/O reads to the LPC bus during
LPC DMA transfer. If clear, I/O reads are locked out during LPC DMA transfers.
LPC Memory Writes during LPC DMA. If set, this bit allows memory writes to the LPC
bus during LPC DMA transfer. If clear, memory writes are locked out during LPC DMA
transfers.
LPC Memory Reads during LPC DMA. If set, this bit allows memory reads to the LPC
bus during LPC DMA transfer. If clear, memory reads are locked out during LPC DMA
transfers.
DIVIL_AC_DMA Bit Descriptions
DIVIL_AC_DMA Register Map
AMD Geode™ CS5535 Companion Device Data Book
Diverse Integration Logic Register Descriptions
RSVD
9
8
7
6
5
4
3
2
1
0