CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 341

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
20 000
Programmable Interval Timer Register Descriptions
6.8
The registers for the Programmable Interval Timer (PIT)
are divided into three sets:
• Standard GeodeLink Device (GLD) MSRs (Shared with
• PIT Specific MSRs
• PIT Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 4.2 "MSR
Addressing" on page 59 for more details.
AMD Geode™ CS5535 Companion Device Data Book
MSR Address
DIVIL, see Section 6.6.1 on page 317.)
I/O Address
51400036h
51400037h
40h
41h
42h
43h
61h
Programmable Interval Timer Register Descriptions
Type
Type
R/W
R/W
R/W
RO
W
W
W
R
R
R
Register Name
PIT Shadow (PIT_SHDW)
PIT Count Enable (PIT_CNTRL)
Width
(Bits)
8
8
8
8
8
8
8
8
Table 6-21. PIT Native Registers Summary
Table 6-20. PIT Specific MSRs Summary
Register Name
PIT Timer 0 Counter - System
(PIT_TMR0_CNTR_SYS)
PIT Timer 0 Status - System
(PIT_TMR0_STS_SYS)
PIT Timer 1 Counter - Refresh
(PIT_TMR1_CNTR_RFSH)
PIT Timer 1 Status - Refresh
(PIT_TMR1_STS_RFSH)
PIT Timer 2 Counter - Speaker
(PIT_TMR2_CNTR_SPKR)
PIT Timer 2 Status - Speaker
(PIT_TMR2_STS_SPKR)
PIT Mode Control Word
(PIT_MODECTL_WORD)
Port B Control (PIT_PORTBCTL)
All MSRs are 64 bits, however, the PIT Specific MSRs are
called out as 8 bits. The PIT treats writes to the upper 56
bits (i.e., bits [63:8]) of the 64-bit MSRs as don’t cares and
always returns 0 on these bits. The PIT Specific MSRs are
summarized in Table 6-20.
The Native registers associated with the PIT are summa-
rized in Table 6-21 and are accessed as I/O Addresses.
The reference column in the tables point to the page where
the register maps and bit descriptions are listed.
Reset Value
Reset Value
31506B
00h
03h
00h
00h
00h
00h
00h
00h
00h
00h
Reference
Reference
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