CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 349

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Programmable Interrupt Controller Register Descriptions
6.9
The registers for the Programmable Interrupt Controller
(PIC) are divided into three sets:
• Standard GeodeLink Device (GLD) MSRs (Shared with
• PIC Specific MSRs
• PIC Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 4.2 "MSR
Addressing" on page 59 for more details.
All MSRs are 64 bits, however, the PIC Specific MSRs are
called out as 32 and 8 bits. The PIC treats writes to the
AMD Geode™ CS5535 Companion Device Data Book
MSR Address
Address
DIVIL, see Section 6.6.1 on page 317.)
51400020h
51400021h
51400022h
51400023h
51400024h
51400025h
51400026h
51400027h
51400034h
020h
0A0h
021h
0A1h
021h
0A1h
021h
0A1h
I/O
Programmable Interrupt Controller Register Descriptions
Type
WO
WO
WO
WO
WO
WO
WO
WO
PIC I/O
Offset
0Ch
1Ch
00h
04h
08h
10h
14h
18h
---
Width
(Bits)
8
8
8
8
8
8
8
8
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
Register Name
Initialization Command Word 1 (PIC_ICW1) - Master
Initialization Command Word 1 (PIC_ICW1) - Slave
Initialization Command Word 2 (PIC_ICW2) - Master
Initialization Command Word 2 (PIC_ICW2) - Slave
Initialization Command Word 3 (PIC_ICW3) - Master
Initialization Command Word 3 (PIC_ICW3) - Slave
Initialization Command Word 4 (PIC_ICW4) - Master
Initialization Command Word 4 (PIC_ICW4) - Slave
Table 6-23. PIC Native Registers Summary
Table 6-22. PIC Specific MSRs Summary
Register Name
IRQ Mapper Unrestricted Y Select Low
(PIC_YSEL_LOW)
IRQ Mapper Unrestricted Y Select High
(PIC_YSEL_HIGH)
IRQ Mapper Unrestricted Z Select Low
(PIC_ZSEL_LOW)
IRQ Mapper Unrestricted Z Select High
(PIC_ZSEL_HIGH)
IRQ Mapper Primary Mask (PIC_IRQM_PRIM)
IRQ Mapper LPC Mask (PIC_IRQM_LPC)
IRQ Mapper Extended Interrupt Request Status
Low (PIC_XIRR_STS_LOW)
IRQ Mapper Extended Interrupt Request Status
High (PIC_XIRR_STS_HIGH)
PIC Shadow (PIC_SHDW)
upper 32/56 bits (i.e., bits [63:32/63:8]) of the 64-bit MSRs
as don’t cares and always returns 0 on these bits.
The PIC Specific MSRs are also accessible in I/O space
via MSR_LBAR_IRQ (MSR 51400008h), except for
MSR_PIC_SHDW (MSR 51400034h). See Section 6.6.2.1
"Local BAR - IRQ Mapper (DIVIL_LBAR_IRQ)" on page
325.
The Native registers associated with the PIC are summa-
rized in Table 6-23 on page 349 and are accessed as I/O
Addresses.
The reference column in the summary tables point to the
page where the register maps and bit descriptions are
listed.
31506B
Reset Value
0000FFFFh
Reset Value
00000000h
00000000h
00000000h
00000000h
00000000h
xxxxxxxxh
xxxxxxxxh
xxh
00h
00h
00h
00h
00h
00h
00h
00h
Reference
Reference
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