CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 36

no-image

CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
20 000
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
13 069
3.2
Information in the tables that follow may have duplicate information in multiple tables. Multiple references all contain identi-
cal information.
3.2.1
36
Signal Name
MHZ66_CLK
MHZ48_CLK
MHZ14_CLK
KHZ32_XCI
KHZ32_XCO
RESET_WORK#
RESET_STAND#
RESET_OUT#
WORKING
Signal Descriptions
System Interface Signals
31506B
Ball No.
N17
A10
C1
A4
B3
C6
B8
A5
C5
Type
Wire
Wire
O
O
I
I
I
I
I
Description
66 MHz Clock. This is the main system clock. It is also used by the IDE
interface.
USB Clock. The 48 MHz clock for the UARTs and SMB Controller.
14.31818 MHz Timer Clock. The input clock for power management
functions and the Programmable Interval Timer (PIT).
32 kHz Input. This input is used for the real-time clock (RTC), GPIOs,
MFGPTs, and power management functions.
This input may come from either an external oscillator or one side of a
32.768 kHz crystal. If an external oscillator is used, it should be pow-
ered by V
External oscillators often do not power up cleanly, causing the Standby
logic to fail to reset properly. If used, it is required that
RESET_STAND# be used to reset the Standby logic after the external
oscillator has stabilized. This can be as long as one second.
32 kHz Input 2. This input is to be connected to the other side of the
crystal oscillator connected to KHZ32_XCI, if used. Leave open (not
connected) if an oscillator (not a crystal) is connected to KHZ32_XCI.
Reset Working Power Domain. This signal, when asserted, is the
master reset for all Geode CS5535 companion device interfaces that
are in the Working power domain. See Section 4.9.1 "Power Domains"
on page 80 for a description of the Working power domain.
RESET_WORK# must be asserted for at least 10 ns in order to be
properly recognized.
If LVD_EN# is enabled (tied low) use of this input is not required. See
the LVD_EN# signal description for further details.
Reset Standby Power Domain. This signal, when asserted, is the
master reset for all Geode CS5535 companion device interfaces that
are in the Standby power domain. See Section 4.9.1 "Power Domains"
on page 80 for a description of the Standby power domain.
To ensure the Skip feature is disabled, PWR_BUT# must be high
before RESET_STAND# is de-asserted. See PWR_BUT# description
in Table 3-9 "GPIOx Available Functions Descriptions" starting on
page 49 for details on the Skip feature.”
If LVD_EN# is enabled (tied low) use of this input is not required. See
the LVD_EN# discussion in this table.
Tie directly to V
Reset Output. This is the main system reset signal. RESET_OUT# is
de-asserted synchronously with the low-to-high edge of PCI_CLK. The
de-assertion is delayed from internal reset by up to 32 seconds, with
an 8 ms default value, using a programmable counter driven by the 32
kHz clock. Note this counter default is established by RESET_STAND#
and is not affected by RESET_WORK#. Therefore, the delay value
may be changed and the system reset with the new value.
Working State. When high, indicates the chip is in the Working state.
This signal is intended to be used to control power to off-chip devices
in a system. Open-drain. External pull-up required.
IO_VSB
IO_VSB
.
AMD Geode™ CS5535 Companion Device Data Book
if not used.
Signal Definitions

Related parts for CS5535-UDCF