CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 366

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.10.2
6.10.2.1 KEL HCE Control Register (KEL_HCE_CTRL)
KEL Memory Offset 100h
Type
Reset Value
366
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:9
Bit
8
7
6
5
4
3
2
1
0
KEL Native Registers
Name
RSVD
A20State
IRQ12Active
IRQ1Active
A20Sequence
ExternalIRQEn
IRQEn
CharacterPending
Emulation
Interrupt (RO)
EmulationEnable
R/W
00000000h
31506B
Description
Reserved. Writes have no effect; reads return 0.
A20 State. Indicates current state of A20 on the LPC keyboard controller. Used to com-
pare against value written to I/O Port 060h when A20Sequence is active. A20State is
set and cleared only by software.
IRQ12 Active. Indicates that a positive transition on IRQ12 from the LPC keyboard
controller has occurred. Software may write 1 to this bit to clear (0) it. A software write
of 0 to this bit has no effect.
IRQ1 Active. Indicates that a positive transition on IRQ1 from the LPC keyboard con-
troller has occurred. Software may write 1 to this bit to clear (0) it. A software write of a
0 to this bit has no effect.
A20 Sequence. Set by KEL when a data value of D1h is written to I/O Port 064h.
Cleared by KEL on write to I/O Port 064h of any value other than D1h.
External Interrupt Request Enable. When set to 1, IRQ1 and IRQ12 from the LPC
keyboard controller causes an Emulation Event. The function controlled by this bit is
independent of the setting of the EmulationEnable bit (bit 0).
Interrupt Request Enable. When set, the KEL generates IRQ1 or IRQ12 as long as
the OutputFull bit in HCE_Status is set to 1. If the AuxOutputFull bit of HceStatus is 0,
then IRQ1 is generated; if it is 1, then an IRQ12 is generated.
Character Pending, When set, an EE is generated when the OutputFull bit of the
HCE_Status register is cleared to 0.
Emulation Interrupt (Read Only). This bit is a static decode of the Emulation Enable
state.
Returns 1 if: CharacterPending = 1
OR InputFull = 1
OR ExternalIRQEn = 1 AND (IRQ1Active OR IRQ12Active = 1).
Emulation Enable. When set to 1, the KEL is enabled for legacy emulation. The KEL
decodes accesses to I/O Port 060h and 064h and generates IRQ1 and/or IRQ12 when
appropriate. Additionally, the KEL generates an ASMI at appropriate times to invoke
the emulation software.
RSVD
KEL_HCE_CTRL Bit Descriptions
KEL_HCE_CTRL Register Map
AMD Geode™ CS5535 Companion Device Data Book
Keyboard Emulation Logic Register Descriptions
9
8
7
6
5
4
3
2
1
0