CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 373

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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System Management Bus Register Descriptions
6.11.1.3 SMB Control Status (SMB_CTRL_STS)
SMB I/O Offset
Type
Reset Value
This register configures and controls the SMB functional block. It maintains the current SMB status and controls several
SMB functions. On reset and when the SMB is disabled, the non-reserved bits of SMBCST are cleared.
AMD Geode™ CS5535 Companion Device Data Book
Bit
7:6
5
4
3
2
1
0
7
Name
RSVD
TGSCL
TSDA (RO)
GCMTCH (RO)
MATCH (RO)
BB (R/W1C)
BUSY (RO)
RSVD
02h
R/W
10h
6
Description
Reserved. Reads return 0; writes have no effect.
Toggle SMB_CLK Line. Enables toggling the SMB_CLK line during error recovery.
0: Clock toggle completed.
1: When the SMB_DATA line is low, writing 1 to this bit toggles the SMB_CLK line for
Test SMB_DATA Line (Read Only). This bit reads the current value of the SMB_DATA
line. It can be used while recovering from an error condition in which the SMB_DATA
line is constantly pulled low by an out-of-sync slave. Data written to this bit is ignored.
Global Call Match (Read Only).
0: Start condition or Repeated Start and a Stop condition (including Illegal Start or
1: In slave mode, GCMEN (SMB I/O Offset 03h[5]) is set and the address byte (the first
Address Match (Read Only).
0: Start condition or Repeated Start and a Stop condition (including Illegal Start or
1: SAEN (SMB I/O Offset 04h[7]) is set and the first 7 bits of the address byte (the first
Bus Busy (Read/Write 1 to Clear).
0: Writing 1, SMB disabled, or Stop condition detected.
1: Bus active (a low level on either SMB_DATA or SMB_CLK), or Start condition.
Busy (Read Only). This bit indicates the SMB is either in slave transmit/receive or
master transmit/receive mode, or if there is an arbitration going on the bus.
0: SMB disabled or SMbus in Idle mode
1: SMB is in one of the following states:
TGSCL
one cycle. Writing 1 to TGSCL while SMB_DATA is high is ignored.
Stop condition).
byte transferred after a Start condition) is 00h.
Stop condition).
byte transferred after a Start condition) match the 7-bit address in the SMBADR
(SMB I/O Offset 04h[6:0]).
-Generating a Start condition.
-Detects a Start condition.
-Master mode (MASTER (SMB I/O Offset 01h[1]) is set).
-Slave mode (MATCH (bit 2) or GCMTCH (bit 3) are set).
5
SMB_CTRL_STS Bit Descriptions
SMB_CTRL_STS Register Map
TSDA
4
GCMTCH
3
MATCH
2
31506B
BB
1
BUSY
0
373

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