CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 374

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.11.1.4 SMB Control 1 (SMB_CTRL1)
SMB I/O Offset
Type
Reset Value
This register configures and controls the SMB functional block. It maintains the current SMB status and controls several
SMB functions. On reset and when the SMB is disabled, the non-reserved bits of SMB_CTRL1 are cleared.
374
STASTRE
Bit
7
6
5
4
3
2
1
7
Name
STASTRE
NMINTE
GCMEN
ACK
RSVD
INTEN
STOP
NMINTE
03h
R/W
00h
6
31506B
Description
Stall After Start Enable.
0: When cleared, STASTR (SMB I/O Offset 01h[3]) can not be set. However, if
1: Stall after start mechanism enabled, and SMB stalls the bus after the address byte.
New Match Interrupt Enable.
0: No interrupt issued on a new match.
1: Interrupt issued on a new match only if INTEN (bit 2) is set.
Global Call Match Enable.
0: SMB not responding to global call.
1: Global call match enabled.
Receive Acknowledge. This bit is ignored in transmit mode. When the device acts as
a receiver (slave or master), this bit holds the transmitting instruction that is transmitted
during the next acknowledge cycle.
0: Cleared after acknowledge cycle.
1: Negative acknowledge issued on next received byte.
Reserved. Reads return 0; writes have no effect.
Interrupt Enable.
0: SMB interrupt disabled.
1: SMB interrupt enabled. An interrupt is generated in response to one of the following
Stop.
0: Automatically cleared after Stop issued.
1: Setting this bit in master mode generates a Stop condition to complete or abort cur-
GCMEN
STASTR is set, clearing STASTRE will not clear STASTR.
events:
-Detection of an address match (NMATCH, SMB I/O Offset 01h[2] = 1) and NMINTE
(bit 6) = 1.
-Receipt of bus error (BER, SMB I/O Offset 01h[5] = 1).
-Receipt of Negative Acknowledge after sending a byte (NEGACK, SMB I/O Offset
01h[4] = 1).
-Acknowledge of each transaction (same as the hardware set of the SDAST bit,
SMB I/O Offset 01h[6]) when DMA not enabled.
-In master mode if STASTRE = 1 (SMB I/O Offset 03h[7]), after a successful start
(STASTR = 1, SMB I/O Offset 01h[3]).
-Detection of a Stop condition while in slave mode (SLVSTP = 1, SMB I/O Offset
01h[7]).
rent message transfer.
5
SMB_CTRL1 Bit Descriptions
SMB_CTRL1 Register Map
ACK
4
RSVD
3
AMD Geode™ CS5535 Companion Device Data Book
System Management Bus Register Descriptions
INTEN
2
STOP
1
START
0