CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 376

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.11.1.6 SMB Control 2 (SMB_CTRL2)
SMB I/O Offset
Type
Reset Value
This register enables/disables the functional block and determines the SMB clock rate.
6.11.1.7 SMB Control 3 (SMB_CTRL3)
SMB I/O Offset
Type
Reset Value
This register enables/disables the functional block and determines the SMB clock rate.
376
Bit
7:1
Bit
7:0
0
7
7
Name
SCLFRQ[6:0]
EN
Name
SCLFRQ[14:7]
05h
R/W
00h
06h
R/W
00h
6
6
31506B
Description
SMB_CLK Frequency. This field combined with SCLFRQ[14:7] in SMB_CTRL3
defines the SMB_CLK period (low and high time) when the device serves as a bus
master. The clock low and high times are defined as follows:
t
where t
SCLFRQ can be programmed to values in the range of 0008h through 7FFFh. Using
any other value has unpredictable results.
The low and high time are generally equal unless two or more devices are driving the
SCL line.
Enable.
0: SMB is disabled, all registers are cleared, and clocks are halted. In the SMBCST
1: SMB is enabled.
Description
SMB_CLK Frequency. This field combined with SCLFRQ[6:0] in SMB_CTRL2 defines
the SMB_CLK period (low and high time) when the device serves as a bus master. See
SMB_CTRL2 for use of this register.
SCLl
register all bits are cleared except the TSDA bit, it reflects the value of SMB_DATA.
5
5
= t
CLK
SCLh
SMB_CTRL2 Bit Descriptions
SMB_CTRL3 Bit Descriptions
SMB_CTRL2 Register Map
SMB_CTRL3 Register Map
is the module input clock cycle.
= 2*SCLFRQ*t
SCLFRQ[6:0]
4
4
SCLFRQ[14:7]
CLK
3
3
AMD Geode™ CS5535 Companion Device Data Book
System Management Bus Register Descriptions
2
2
1
1
EN
0
0