CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 383
CS5535-UDCF
Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.CS5535-UDCF.pdf
(579 pages)
Specifications of CS5535-UDCF
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Part Number:
CS5535-UDCF
Manufacturer:
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UART and IR Port Register Descriptions
6.12.2
Eight register banks, each containing eight registers, con-
trol UART/IR operation. All registers use the same 8-byte
address space to indicate I/O Offsets 00h-07h. The active
bank must be selected by the software.
The register bank organization enables access to the
banks, as required for activation of all module modes, while
maintaining transparent compatibility with 16450 or 16550
software. This activates only the registers and specific bits
used in those devices.
The Bank Select Register (BSR) selects the active bank
and is common to all banks. Therefore, each bank defines
seven new registers. See Figure 6-1.
The default bank selection after the system reset is 0, plac-
ing the module in UART 16550 mode. Additionally, setting
the baud in Bank 1 (as required to initialize the 16550
UART) switches the module to non-extended UART mode.
This ensures that running existing 16550 software switches
the system to the 16550 configuration without software
modification.
Table 6-31 shows the main functions of the registers in
each bank. Banks 0 to 3 control UART and IR modes of
operation; Banks 4 to 7 control and configure the IR modes
only. Banks 4 to 7 are reserved in UART2.
AMD Geode™ CS5535 Companion Device Data Book
Bank
0
1
2
3
4
5
6
7
UART/IR Controller Native Registers
UART
x
x
x
x
IR Mode
x
x
x
x
x
x
x
x
Main Functions
Global control and status
Legacy bank
Alternative baud generator divisor, extended control, and status
Module revision ID and shadow registers
IR mode setup
IR control
IR physical layer configuration
CEIR and optical transceiver configuration
Table 6-31. Register Bank Summary
Figure 6-1. UART Register Bank Architecture
I/O Offset 07h
I/O Offset 06h
I/O Offset 05h
I/O Offset 04h
I/O Offset 02h
I/O Offset 01h
I/O Offset 00h
LCR/BSR
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
16550 Banks
31506B
Bank 6
Bank 7
Common
Register
Throughout
All Banks
383
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