CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 384

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.12.3
In non-extended modes of operation, Bank 0 is compatible with both the 16450 and 16550. Upon reset, this functional block
defaults to the 16450 mode. In extended mode, all the registers (except RXD and TXD) offer additional features. The bit
formats for the registers in Bank 0 are summarized in Table 6-32. Detailed descriptions of each register follow.
Note 1.
Note 2.
6.12.3.1 Receive/Transmit Data Ports
Receive Data Port (RXD)
I/O Offset
Type
Reset Value
The RXD (RO) and TXD (WO) ports share the same address.
RXD is accessed during CPU read cycles. It is used to receive incoming data when the FIFOs are disabled, or from the bot-
tom of the RX_FIFO when the FIFOs are enabled.
TXD is accessed during CPU write cycles. It is used to write data directly to the transmitter when the FIFOs are disabled, or
to the TX_FIFO when the FIFOs are enabled.
DMA cycles always access the TXD and RXD ports, regardless of the selected bank.
384
Offset Name
00h
00h
01h
02h
03h
04h
05h
06h
07h
I/O
IER
(Note 1)
IER
(Note 2)
EIR
(Note 1)
EIR
(Note 2)
FCR
BSR
MCR
(Note 1)
MCR
(Note 2)
MSR
(Note 1)
ASCR
(Note 2)
RXD
TXD
LCR
LSR
SPR
Non-Extended Mode.
Extended Mode.
Bank 0 Register Descriptions
00h
RO
xxh
ER_INF
31506B
BKSE
RXD7
TXD7
BKSE
DCD
CTE
7
RXFTH[1:0]
FEN[1:0]
RSVD
RSVD
MDSL[2:0]
TXEMP
SBRK
RSVD
TXUR
RXD6
TXD6
RI
6
Table 6-32. Bank 0 Register Bit Map
RSVD
TXEMP_EV
TXEMP_IE
RXACT
TXRDY
RXD5
STKP
TXD5
DSR
5
TXFTH[1:0]
RSVD
DMA_EV
RXWDG
DMA_IE
IR_PLS
LOOP
RXD4
TXD4
BRK
CTS
EPS
Transmit Data Port (TXD)
I/O Offset
Type
Reset Value
4
Scratch Data
AMD Geode™ CS5535 Companion Device Data Book
BSR[6:0]
TX_DFR
MS_EV
ISEN or
DCDLP
MS_IE
MS_IE
DDCD
RXD3
RSVD
RSVD
TXD3
RXFT
PEN
FE
3
00h
WO
xxh
UART and IR Port Register Descriptions
TXHLT_EV
DMA_EN
LS_EV/
S_OET
RXD2
LS_IE
LS_IE
TXSR
TXD2
RILP
TERI
STB
PE
2
IPR[1:0]
TXLDL_EV
TXLDL_IE
TXLDL_IE
DDSR
RXSR
RSVD
RXD1
TXD1
RTS
RTS
OE
1
WLS[1:0]
RXF_TOUT
RXHDL_IE
RXHDL_IE
RXHDL_IE
FIFO_EN
RXDA
DCTS
RXD0
TXD0
DTR
DTR
IPF
0