CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 387

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

UART and IR Port Register Descriptions
AMD Geode™ CS5535 Companion Device Data Book
Bit
7:6
5
4
3
2
1
0
Name
RSVD
TXEMP_EV
DMA_EV
MS_EV
LS_EV/TXHLT_EV
TXLDL_EV
RXHDL_EV
Description
Reserved. Read as 0.
Transmitter Empty Event. This bit is the same as bit 6 of the LSR (Length Status
Register). It is set to 1 when the transmitter is empty. (Default = 1.)
DMA Event. This bit is set to 1 when a DMA terminal count (TC) is activated. It is
cleared upon read.
Modem Status Event.
• In UART mode:
• In any IR mode:
Link Status Event
• In UART, Sharp-IR and SIR:
Link Status Event or Transmitter Halted Event
• In CEIR:
Note:
Transmitter Low-Data-Level Event. (Default = 1.)
• FIFOs disabled:
• FIFOs enabled:
Receiver High-Data-Level Event.
• FIFOs disabled:
• FIFOs enabled:
EIR Extended Mode Bit Descriptions
— This bit is set to 1 when any of the 0 to 3 bits in the MSR is set to 1.
— The function of this bit depends on the setting of IRMSSL of the IRCR2
— This bit is set to 1 when a receiver error or break condition is reported. When
— Set to 1 when the receiver is overrun or the transmitter underrun.
— Set to 1 when the transmitter holding register is empty.
— Set to 1 when the TX_FIFO level is below the threshold level.
— Set to 1 when a character is in the receiver holding register.
— Set to 1 when the RX_FIFO is equal to or above threshold or an RX_FIFO
register (see Section 6.12.8.2 "IR Control Register 2 (IRCR2)" on page 407).
When IRMSSL is 0, the bit functions as a modem status interrupt event;
when IRMSSL is set to 1, the bit is forced to 0.
FIFOs are enabled, the parity error, frame error and break conditions are
reported only when the associated character reaches the bottom of the
RX_FIFO. An overrun error is reported as soon as it occurs.
timeout has occurred.
A high-speed CPU can service the interrupt generated by the last frame
byte reaching the RX_FIFO bottom before that byte is transferred to mem-
ory by the DMA controller. This can happen when the CPU interrupt
latency is shorter than the RX_FIFO timeout. A DMA request is generated
only when the RX_FIFO level reaches the DMA threshold or when a FIFO
timeout occurs, in order to minimize the performance degradation due to
DMA signal handshake sequences. If the DMA controller must be set up
before receiving each frame, the software in the interrupt routine should
make sure that the last byte of the frame received has been transferred to
memory before reinitializing the DMA controller, otherwise that byte could
appear as the first byte of the next frame received.
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