CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 389

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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UART and IR Port Register Descriptions
FIFO Control Register (FCR)
I/O Offset
Type
Reset Value
The FIFO Control Register (FCR) is used to enable the FIFOs, clear the FIFOs and set the interrupt threshold levels for the
RX_FIFO and TX_FIFO. FCR can be read through SH_FCR in Bank 3, I/O Offset 02h (see Section 6.12.6.3 on page 406).
AMD Geode™ CS5535 Companion Device Data Book
Bit
7:6
5:4
3
2
1
0
7
RXFTH
Name
RXFTH
TXFTH[1:0]
RSVD
TXSR
RXSR
FIFO_EN
02h
WO
00h
6
Description
RX_FIFO Interrupt Threshold Level. These bits select the RX_FIFO interrupt threshold
level. An interrupt is generated when the level of data in the RX_FIFO is equal to or above
the encoded threshold.
00:
01:
10:
11:
TX_FIFO Interrupt Threshold Level. In non-extended modes, these bits have no effect.
In extended modes, these bits select the TX_FIFO interrupt threshold level. An interrupt is
generated when the level of data in the TX_FIFO drops below the encoded threshold.
00:
01:
10:
11:
Reserved. Write to 0.
Transmitter Soft Reset. Writing a 1 to this bit generates a transmitter soft reset that clears
the TX_FIFO and the transmitter logic. This bit is automatically cleared by the hardware.
Receiver Soft Reset. Writing a 1 to this bit generates a receiver soft reset that clears the
RX_FIFO and the receiver logic. This bit is automatically cleared by the hardware.
FIFO_EN (FIFO Enable). When set to 1, this bit enables both the TX_FIFO and
RX_FIFOs. Resetting this bit clears both FIFOs. In CEIR mode, the FIFOs are always
enabled and the setting of this bit is ignored.
5
(16-Level FIFO)
1 (Default)
4
8
14
(16-Level FIFO)
1 (Default)
3
9
13
RX_FIFO Interrupt Threshold Level
TX_FIFO Interrupt Threshold Level
TXFTH
FCR Bit Descriptions
FCR Register Map
4
RSVD
(32-Level FIFO)
1 (Default)
8
16
26
(32-Level FIFO)
1 (Default)
7
17
25
3
TXSR
2
31506B
RXSR
1
FIFO_EN
0
389

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