CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 397

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

UART and IR Port Register Descriptions
6.12.3.8 Scratchpad/Auxiliary Status and Control Registers
The Scratchpad Register (SPR) and Auxiliary Status and Control Register (ASCR) share the same address.
Scratchpad Register (SPR)
I/O Offset
Type
Reset Value
This register is accessed when the device is in non-extended mode (EXCR1.EXT_SL = 0). This is a scratchpad register for
temporary data storage.
Auxiliary Status and Control Register (ASCR)
I/O Offset
Type
Reset Value
ASCR is accessed when the extended mode (EXCR1.EXT_SL = 1) of operation is selected. The definition of the bits in this
case is dependent upon the mode selected in the MCR, bits 7 to 5. This register is cleared upon hardware reset. Bit 2 is
also cleared when the transmitter is “soft reset” (via the FIFO Control register) or after the S_EOT byte is transmitted. Bit 6
is also cleared when the transmitter is “soft reset” or by writing 1 into it. Bits 0, 1, 4, and 5 are also cleared when the
receiver is “soft reset” (via the FIFO Control register).
AMD Geode™ CS5535 Companion Device Data Book
Bit
7
6
5
4
3
2
1
0
RSVD
7
Name
RSVD
TXUR
RXACT
RXWDG
RSVD
S_EOT
RSVD
RXF_TOUT
(RO)
07h
R/W
00h
07h
R/W
00h
TXUR
6
Description
Reserved. Write as 0.
IR Transmitter Underrun. For CEIR mode only. This bit is set to 1 when a transmitter
underrun occurs. It is always cleared when a mode other than CEIR is selected. This bit
must be cleared, by writing a 1 into it to re-enable transmission.
Receiver Active. For CEIR mode only. This bit is set to 1 when an IR pulse or pulse-train is
received. If a 1 is written into this bit position, the bit is cleared and the receiver deactivated.
When this bit is set, the receiver samples the IR input continuously at the programmed
baud and transfers the data to the RX_FIFO.
Reception WATCHDOG. For CEIR mode only. This bit is set to 1 each time a pulse or
pulse-train (modulated pulse) is detected by the receiver. It can be used by the software to
detect a receiver idle condition. It is cleared upon read.
Reserved. Write as 0.
Set End of Transmission. For CEIR mode only. When a 1 is written into this bit position
before writing the last character into the TX_FIFO, data transmission is properly completed.
If the CPU simply stops writing data into the TX_FIFO at the end of the data stream, a
transmitter underrun is generated and the transmitter stops. In this case this is not an error,
but the software must clear the underrun before the next transmission can occur. This bit is
automatically cleared by hardware when a character is written to the TX_FIFO.
Reserved. Write as 0.
RX_FIFO Timeout (Read Only). This bit is set to 1 if the RX_FIFO is below threshold and
an RX_FIFO timeout occurs. It is cleared when a character is read from the RX_FIFO.
RXACT
5
ASCR Extended Mode Bit Descriptions
ASCR Extended Mode Register Map
RXWDG
4
RSVD
3
S_EOT
2
31506B
RSVD
1
RXF_TOUT
0
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