CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 403

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

UART and IR Port Register Descriptions
6.12.5.3 Bank Select Register (BSR)
I/O Offset
Type
Reset Value
BSR is the same as the BSR register at I/O Offset 03h in Bank 0. See Section 6.12.3.4 "Link Control/Bank Select Regis-
ters" on page 390 for bit descriptions.
6.12.5.4 Extended Control Register 2 (EXCR2)
I/O Offset
Type
Reset Value
EXCR2 configures the RX_FIFO and TX_FIFO sizes and the value of the prescaler, and controls the baud divisor register
lock. Upon reset, all bits are set to 0.
AMD Geode™ CS5535 Companion Device Data Book
Bit
5:4
3:2
1:0
7
6
LOCK
7
Name
LOCK
RSVD
PRESL[1:0]
RF_SIZ[1:0]
TF_SIZ[1:0]
03h
R/W
00h
04h
R/W
00h
RSVD
6
Description
Baud Divisor Register Lock. When set to 1, any access to the baud generator divisor
register through LBGD_L and LBGD_H, as well as fallback are disabled from non-
extended mode. In this case, two scratchpad registers overlaid with LBGD_L and
LBGD_H are enabled, and any attempted CPU access of the baud generator divisor reg-
ister through LBGD_L and LBGD_H access the scratchpad registers instead. This bit
must be set to 0 when extended mode is selected.
Reserved. Write as 0.
Prescaler Select. The prescaler divides the 24 MHz input clock frequency to provide the
clock for the baud generator.
00: 13 (Default)
01: 1.625
10: Reserved
11: 1.0
RX_FIFO Levels Select. These bits select the number of levels for the RX_FIFO. They
are effective only when the FIFOs are enabled. (FCR bit 0 = 1.)
00: 16 (Default)
01: 32
1x: Reserved
TX_FIFO Levels Select. These bits select the number of levels for the TX_FIFO. They
are effective only when the FIFOs are enabled. (FCR bit 0 = 1.)
00: 16 (Default)
01: 32
1x: Reserved
5
PRESL[1:0]
EXCR2 Bit Descriptions
EXCR2 Register Map
4
3
RF_SIZ[1:0]
2
31506B
1
TF_SIZ[1:0]
0
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