CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 407

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

UART and IR Port Register Descriptions
6.12.7.2 Bank Select Register (BSR)
I/O Offset
Type
Reset Value
BSR is the same as the BSR register at I/O Offset 03h in Bank 0. See Section 6.12.3.4 "Link Control/Bank Select Regis-
ters" on page 390 for bit descriptions.
6.12.8
The bit formats for the registers in Bank 5 are summarized in Table 6-43. Detailed descriptions of each register follow.
6.12.8.1 Bank Select Register (BSR)
I/O Offset
Type
Reset Value
BSR is the same as the BSR register at I/O Offset 03h in Bank 0. See Section 6.12.3.4 "Link Control/Bank Select Regis-
ters" on page 390 for bit descriptions.
6.12.8.2 IR Control Register 2 (IRCR2)
I/O Offset
Type
Reset Value
IRCR2 controls the basic settings of the IR modes. Upon reset, the content of this register is 02h.
AMD Geode™ CS5535 Companion Device Data Book
00h-02h
05h-07h
Offset
03h
04h
I/O
Bit
7:5
3:2
RSVD
4
1
0
7
Register
Bank 5 Register Descriptions
Name
RSVD
BSR
IRCR2
RSVD
Name
RSVD
AUX_IRRX
RSVD
IRMSSL
IR_FDPLX
03h
R/W
00h
03h
R/W
00h
04h
R/W
02h
RSVD
6
RSVD
BKSE
7
Description
Reserved. Write to 0.
Auxiliary IR Input Select. When set to 1, the IR signal is received from the auxiliary
input. See Table 6-51 "IR Receive Input Selection" on page 416.
Reserved. Write to 0.
MSR Register Function Select in IR Mode. This bit selects the behavior of the MSR
and Modem Status Interrupt (MS_EV) when an IR mode is selected. When a UART
mode is selected, the MSR and the MS_EV function normally and this bit is ignored.
0: MSR and MS_EV work in the IR modes as in the UART mode.
1: MSR returns 30h, and MS_EV is disabled (Default).
Enable IR Full Duplex Mode. When set to 1, the IR receiver is not masked during trans-
mission.
RSVD
5
RSVD
6
Table 6-43. Bank 5 Bit Map
IRCR2 Bit Descriptions
AUX_IRRX
IRCR2 Register Map
RSVD
4
5
AUX_IRRX
RSVD
4
3
RSVD
RSVD
Bits
BSR[6:0]
RSVD
3
RSVD
2
RSVD
31506B
2
IRMSSL
1
IRMSSL
1
IR_FDPLX
IR_FDPLX
0
0
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