CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 409

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

UART and IR Port Register Descriptions
6.12.9.2 SIR Pulse Width Register (SIR_PW)
I/O Offset
Type
Reset Value
SIR_PW sets the pulse width for transmitted pulses in SIR operation mode. These settings do not affect the receiver. Upon
reset, the content of this register is 00h, which defaults to a pulse width of 3/16 of the baud rate.
6.12.9.3 Bank Select Register (BSR)
I/O Offset
Type
Reset Value
BSR is the same as the BSR register at I/O Offset 03h in Bank 0. See Section 6.12.3.4 "Link Control/Bank Select Regis-
ters" on page 390 for bit descriptions.
AMD Geode™ CS5535 Companion Device Data Book
Bit
7:4
3:0
7
Name
RSVD
SPW[3:0]
02h
R/W
00h
03h
R/W
00h
6
RSVD
Description
Reserved. Write to 0.
SIR Pulse Width. Two codes for setting the pulse width are available. All other values for
this field are reserved.
0000: Pulse width = 3/16 of bit period (Default).
1101: Pulse width = 1.6 µs.
5
SIR_PW Bit Descriptions
SIR_PW Register Map
4
3
2
SPW[3:0]
31506B
1
0
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