CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 417

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Direct Memory Access Register Descriptions
6.13
The registers for the Direct Memory Access (DMA) are
divided into three sets:
• Standard GeodeLink Device (GLD) MSRs (Shared with
• DMA Specific MSRs
• DMA Native Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 4.2 "MSR
Addressing" on page 59 for more details.
AMD Geode™ CS5535 Companion Device Data Book
MSR Address
DIVIL, see Section 6.6.1 on page 317.)
I/O Address
51400040h
51400041h
51400045h
51400046h
51400047h
51400048h
51400049h
51400042
51400043
51400044
000h
001h
002h
003h
004h
Direct Memory Access Register Descriptions
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
Register Name
DMA Mapper (DMA_MAP)
DMA Shadow Channel 0 Mode
(DMA_SHDW_CH0)
DMA Shadow Channel 1 Mode
(DMA_SHDW_CH1)
DMA Shadow Channel 2 Mode
(DMA_SHDW_CH2)
DMA Shadow Channel 3 Mode
(DMA_SHDW_CH3)
DMA Shadow Channel 4 Mode
(DMA_SHDW_CH4]
DMA Shadow Channel 5 Mode
(DMA_SHDW_CH5)
DMA Shadow Channel 6 Mode
(DMA_SHDW_CH6)
DMA Shadow Channel 7 Mode
(DMA_SHDW_CH7)
DMA Shadow Mask (DMA_MSK_SHDW)
Width
(Bits)
8
8
8
8
8
Table 6-53. DMA Native Registers Summary
Table 6-52. DMA Specific MSRs Summary
Register Name
Slave DMA Channel 0 Memory Address
(DMA_CH0_ADDR_BYTE)
Slave DMA Channel 0 Transfer Count
(DMA_CH0_CNT_BYTE)
Slave DMA Channel 1 Memory Address
(DMA_CH1_ADDR_BYTE)
Slave DMA Channel 1 Transfer Count
(DMA_CH1_CNT_BYTE)
Slave DMA Channel 2 Memory Address
(DMA_CH2_ADDR_BYTE)
All MSRs are 64 bits, however, the DMA Specific MSRs
(summarized in Table 6-52) are called out as 16 bits. The
DMA module treats writes to the upper 48 bits (i.e., bits
[63:16]) of the 64-bit MSRs as don’t cares and always
returns 0 on these bits.
The Native registers associated with the DMA module are
summarized in Table 6-53 and accessed as I/O Addresses.
The reference column in the summary tables point to the
page where the register maps and bit descriptions are
listed.
Reset Value
0000h
00FFh
00xxh
00xxh
00xxh
00xxh
00xxh
00xxh
00xxh
00xxh
31506B
Reset Value
xxh
xxh
xxh
xxh
xxh
Reference
Reference
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