CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 42

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.2.3.2
42
Signal Name
NOR Flash / GPCS Mode
FLASH_CS[3:0]#
FLASH_RE#
FLASH_WE#
FLASH_ALE
FLASH_AD[27:26]/
AD[2:1],
FLASH_AD25/
AD0,
FLASH_AD[24:18]/
AD[9:3]
FLASH_AD[17:10]/
IO[7:0]
FLASH_IOCHRDY
NAND Flash Mode
FLASH_CE[3:0]#
FLASH_RE#
FLASH_WE#
FLASH_ALE
FLASH_CLE
FLASH_IO[7:0]
FLASH_RDY/BUSY#
Flash Controller Interface
31506B
C17, D16,
C16, C15,
C16, C15,
C12, A14,
B11, A12,
A11, B15,
B16, A17,
E16, E15,
D15, B17,
C12, A14,
E16, E15,
D15, B17,
C10, B10
D17, E17
A15, B14
C10, B10
A15, B14
Ball No.
C13
C13
B13
C14
A13
B13
C14
A11
A13
Type
I/O
I/O
O
O
O
O
O
O
O
O
O
O
I
I
Description
Chip Selects. Combine with FLASH_RE#/WE# strobes to access
external NOR Flash devices or some simple devices such as a UART.
CS3# is dedicated to a boot Flash device.
Note:
Read Enable Strobe. This signal is asserted during read operations
from the NOR array.
Write Enable Strobe. This signal is asserted during write operations
to the NOR array.
Address Latch Enable. Controls external latch (e.g., 74x373) for
latching the higher address bits in address phase.
Address Bus. During the address phase, address [27:18] is put on
the bus. During the data phase, address [9:0] is put on the bus.
Multiplexed Address and I/O Bus. During the address phase, NOR
address [17:10] are placed on these lines. During the data phase, it is
the NOR I/O data bus.
I/O Channel Ready. When a device on the bus wants to extend its
current cycle, it pulls this signal low to insert the wait state.
Chip Enables. These signals remain low during a NAND cycle.
Note:
Read Enable Strobe. This signal is asserted during read operations
from the NAND array.
Write Enable Strobe. This signal is asserted during write operations
to the NAND array.
Address Latch Enable. Level signal to indicate an address byte is
writing to the NAND Flash device.
Command Latch Enable. Indicates a command byte is being written
to the device.
I/O Bus. I/O bus for NAND Flash devices. Command, address, and
data are sent on this bus. This bus is actively driven to zero with or
without an LPC_CLK from and after reset.
Ready/Busy#. NAND Flash pulls this signal low to indicate it is busy
with an internal operation. No further action is accepted except read
status.
Ball A14 is the only ball that changes direction from IDE to
Flash (input when in IDE mode, output when in Flash mode).
If this interface is to be switched between IDE and Flash
modes, the IDE interface must only use PIO mode and ball
A14 requires a pull-up resistor to keep FLASH_CS3# high
when in IDE mode.
Ball A14 is the only ball that changes direction from IDE to
Flash. Needs external pull-up for Flash use.
AMD Geode™ CS5535 Companion Device Data Book
Signal Definitions