CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 469

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GPIO Subsystem Register Descriptions
6.16.2.20 GPIO/AUX Lock Enable (GPIO[x]_LOCK_EN
These registers lock the values of feature bit registers except the GPIO[x]_READ_BACK, GPIO[x]_IN_POSEDGE_STS,
and GPIO[x]_IN_NEGEDGE_STS registers. When set, the indicated feature bits may not be changed. The
GPIO[x]_LOCK_EN registers are not based on the atomic programming model (i.e., only one bit for control as opposed to
two bits).
GPIO Low Bank Lock Enable (GPIOL_LOCK_EN)
GPIO I/O Offset
Type
Reset Value
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:15
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
RSVD
LKNE
LKPE
LKIP
LKIA
LKEE
LKFE
LKII
LKIE
LKPD
LKPU
LKA2
LKA1
LKOI
LKOD
LKOE
LKOV
3Ch
R/W
00000000h
RSVD
Description
Reserved. Write to 0.
Lock GPIOL_IN_NEGEDGE_EN. When set, writing to the GPIO Low Bank Input Neg-
ative Edge Enable register (GPIO I/O Offset 44h) is prevented.
Lock GPIOL_IN_POSEDGE_EN. When set, writing to the GPIO Low Bank Input Posi-
tive Edge Enable register (GPIO I/O Offset 40h) is prevented.
Lock GPIOL_EVENTS_EN. When set, writing to the GPIO Low Bank Events Enable
(interrupts &PMEs) register (GPIO I/O Offset 38h) is prevented.
Lock GPIOL_IN_AUX1_SEL. When set, writing to the GPIO Low Bank Input Auxiliary
1 Select register (GPIO I/O Offset 34h) is prevented.
Lock GPIOL_IN_EVNTCNT_EN. When set, writing to the GPIO Low Bank Input Event
Count Enable register (GPIO I/O Offset 2Ch) is prevented.
Lock GPIOL_IN_FLTR_EN. When set, writing to the GPIO Low Bank Input Filter
Enable register (GPIO I/O Offset 28h) is prevented.
Lock GPIOL_IN_INVRT_EN. When set, writing to the GPIO Low Bank Input Invert
Enable register (GPIO I/O Offset 24h) is prevented.
Lock GPIOL_IN_EN. When set, writing to the GPIO Low Bank Input Enable register
(GPIO I/O Offset 20h) is prevented.
Lock GPIOL_PU_EN. When set, writing to the GPIO Low Bank Pull-Down Enable reg-
ister (GPIO I/O Offset 1Ch) is prevented.
Lock GPIOL_PU_EN. When set, writing to the GPIO Low Bank Pull-Up Enable register
(GPIO I/O Offset 18h) is prevented.
Lock GPIOL_OUT_AUX2_SEL. When set, writing to the GPIO Low Bank Output Auxil-
iary 2 Select register (GPIO I/O Offset 14h) is prevented.
Lock GPIOL_OUT_AUX1_SEL. When set, writing to the GPIO Low Bank Output Auxil-
iary 1 Select register (GPIO I/O Offset 10h) is prevented.
Lock GPIOL_OUT_INVRT_EN. When set, writing to the GPIO Low Bank Output Invert
Enable register (GPIO I/O Offset 0Ch) is prevented.
Lock GPIOL_OUT_OD_EN. When set, writing to the GPIO Low Bank Output Open-
Drain Enable register (GPIO I/O Offset 08h) is prevented.
Lock GPIOL_OUT_EN. When set, writing to the GPIO Low Bank Enable register
(GPIO I/O Offset 04h) is prevented.
Lock GPIOL_OUT_VAL. When set, writing to the GPIO Low Bank Output Value regis-
ter (GPIO I/O Offset 00h) is prevented.
GPIOL_LOCK_ENABLE Bit Descriptions
GPIOL_LOCK_EN Register Map
9
8
31506B
7
6
5
4
3
2
1
469
0