CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 483

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Multi-Function General Purpose Timer Register Descriptions
6.17
The registers for the Multi-Function General Purpose Timer
(MFGPT) are divided into three sets:
• Standard GeodeLink Device (GLD) MSRs (Shared with
• MFGPT Specific MSRs
• MFGPT Native Registers.
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 4.2 "MSR
Addressing" on page 59 for more details.
AMD Geode™ CS5535 Companion Device Data Book
MSR Address
I/O Offset
DIVIL, see Section 6.6.1 on page 317.)
MFGPT
5140002Ah
5140002Bh
51400028h
51400029h
0Ch
1Ch
0Ah
0Eh
1Ah
1Eh
00h
02h
04h
06h
08h
10h
12h
14h
16h
18h
20h
22h
24h
Multi-Function General Purpose Timer Register Descriptions
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/W
R/W
R/W
WO
Width
(Bits)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Register Name
MFGPT IRQ Mask (MFGPT_IRQ)
MFGPT NMI and Reset Mask (MFGPT_NR)
MFGPT Reserved (MFGPT_RSVD)
MFGPT Clear Setup Test (MFGPT_SETUP)
Table 6-65. MFGPT Native Registers Summary
Table 6-64. MFGPT Specific MSRs Summary
Register Name
MFGPT0 Comparator 1 (MFGPT0_CMP1)
MFGPT0 Comparator 2 (MFGPT0_CMP2)
MFGPT0 Up Counter (MFGPT0_CNT)
MFGPT0 Setup (MFGPT0_SETUP)
MFGPT1 Comparator 1 (MFGPT1_CMP1)
MFGPT1 Comparator 2 (MFGPT1_CMP2)
MFGPT1 Up Counter (MFGPT1_CNT)
MFGPT1 Setup (MFGPT1_SETUP)
MFGPT2 Comparator 1 (MFGPT2_CMP1)
MFGPT2 Comparator 2 (MFGPT2_CMP2)
MFGPT2 Up Counter (MFGPT2_CNT)
MFGPT2 Setup (MFGPT2_SETUP)
MFGPT3 Comparator 1 (MFGPT3_CMP1)
MFGPT3 Comparator 2 (MFGPT3_CMP2)
MFGPT3 Up Counter (MFGPT3_CNT)
MFGPT3 Setup (MFGPT3_SETUP)
MFGPT4 Comparator 1 (MFGPT4_CMP1)
MFGPT4 Comparator 2 (MFGPT4_CMP2)
MFGPT4 Up Counter (MFGPT4_CNT)
All MSRs are 64 bits, however, the MFGPT Specific MSRs
(summarized in Table 6-64) are called out as 32 bits. The
MFGPT module treats writes to the upper 32 bits (i.e., bits
[63:32]) of the 64-bit MSRs as don’t cares and always
returns 0 on these bits.
The Native registers associated with the MFGPT (summa-
rized in Table 6-65) are accessed via a Base Address Reg-
ister, MSR_LBAR_MFGPT (MSR 5140000Dh), as I/O
Offsets. (See Section 6.6.2.6 on page 329 for bit descrip-
tions of the Base Address Register.)
The reference column in the summary tables point to the
page where the register maps and bit descriptions are
listed.
Reset Value
31506B
00000000h
00000000h
00000000h
00000000h
Reset Value
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Reference
Reference
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