CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 494

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.18
The registers for the Power Management Controller (PMC)
are divided into four sets:
• Standard GeodeLink Device (GLD) MSRs (Shared with
• PMC Specific MSRs
• ACPI Registers
• PM Support Registers
The MSRs are accessed via the RDMSR and WRMSR pro-
cessor instructions. The MSR address is derived from the
perspective of the CPU Core. See Section 4.2 "MSR
Addressing" on page 59 for more details.
All MSRs are 64 bits, however, the PMC Specific MSRs
(summarized in Table 6-66) are called out as 32 bits. The
PMC module treats writes to the upper 32 bits (i.e., bits
[63:32]) of the 64-bit MSRs as don’t cares and always
returns 0 on these bits.
Note 1. Required ACPI register.
Note 2. Both PM1_STS and PM1_EN access Offset 00h when using 32-bit access.
Note 3. SSMI may be implemented on this register by decode hardware outside of PM module.
Note 4. Optional ACPI register. SSMI may be implemented on this register by decode hardware outside of PM module.
Note 5. Required ACPI register that can also be implemented via a control method.
494
51400050h
51400051h
I/O Offset
Address
DIVIL, see Section 6.6.1 on page 317.)
(WORD
access
MSR
ACPI
only)
0Ch
1Ch
00h
04h
08h
10h
14h
18h
Only PM1_STS with a 16-bit access to Offset 00h.
Only PM1_EN with a 16-bit access to Offset 02h.
Offset 04h is reserved. Reads return 0.
Power Management Controller Register Descriptions
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
RO
R/W
R/W
31506B
Width
(Bits)
Register Name
PMC Logic Timer (PMC_LTMR)
PMC Reserved (PMC_RSVD)
16
16
16
16
32
32
32
32
Register Name
PM Status 1 (PM1_STS) (Note 1 and Note 2)
PM Enable 1 (PM1_EN) (Note 1 and Note 2)
PM Control 1 (PM1_CNT) (Note 1 and
Note 3)
PM Control 2 (PM2_CNT) (Note 4)
PM Timer (PM_TMR) (Note 1)
PM Reserved (PM_RSVD)
General Purpose Events Status 0
(PM_GPE0_STS) (Note 5)
General Purpose Events Enable 0
(PM_GPE0_EN) (Note 5)
Table 6-66. PMC Specific MSRs Summary
Table 6-67. ACPI Registers Summary
The configuration registers associated with the PMC are
divided into two categories: ACPI registers (summarized in
Table 6-67) and PM Support registers (summarized in
Table 6-68 on page 495):
• The ACPI registers are accessed via Base Address
• The PM Support registers are accessed via a Base
The reference column in the summary tables point to the
page where the register maps and bit descriptions are
listed.
Register, MSR_LBAR_ACPI (MSR 5140000Eh), as I/O
Offsets. (See Section 6.6.2.7 on page 330 for bit
descriptions of the Base Address Register.)
Address Register, MSR_LBAR_PMS (MSR
5140000Fh), as I/O Offsets. (See Section 6.6.2.8 on
page 331 for bit descriptions of the Base Address
Register.)
AMD Geode™ CS5535 Companion Device Data Book
Power Management Controller Register Descriptions
No f/flops
Domain
Working
Power
No f/flops
Domain
Standby
Standby
Working
Working
Working
Standby
Standby
Power
00000000h
00000000h
00000000h
00000000h
Reset
Value
Reset
0000h
0100h
0000h
0000h
0000h
0000h
Value
Reference
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Reference
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